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https://github.com/portapack-mayhem/mayhem-firmware.git
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Preserve radio mode when updating iq_tx_phase_cal (#2008)
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6e34343bde
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8383363e74
@ -150,6 +150,8 @@ void MAX2837::init() {
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}
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void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
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Mode saved_mode = get_mode();
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/* TX IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
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// TX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,0,1 (5dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
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@ -172,7 +174,7 @@ void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
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_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (1 = Chip select enable )
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flush_one(Register::SPI_EN);
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set_mode(Mode::Standby); // Back 3 logic pins CALIBRATION mode -> Standby.
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set_mode(saved_mode); // restore original mode
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}
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enum class Mask { // There are class Mask ,and class mode with same names, but they are not same.
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@ -205,12 +207,18 @@ Mask mode_mask(const Mode mode) { // based on enum Mode cases, we set up the co
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}
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void MAX2837::set_mode(const Mode mode) { // We set up the 3 Logic Pins ENABLE, RXENABLE, TXENABLE accordingly to the max2837 mode case, that we want to set up .
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_mode = mode;
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Mask mask = mode_mask(mode);
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gpio_max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
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gpio_max2837_rxenable.write(toUType(mask) & toUType(Mask::RxEnable));
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gpio_max2837_txenable.write(toUType(mask) & toUType(Mask::TxEnable));
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}
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Mode MAX2837::get_mode() {
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return _mode;
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}
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void MAX2837::flush() {
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if (_dirty) {
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for (size_t n = 0; n < reg_count; n++) {
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@ -841,6 +841,7 @@ class MAX2837 : public MAX283x {
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private:
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spi::arbiter::Target& _target;
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Mode _mode{Mode::Standby};
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RegisterMap _map{initial_register_values};
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DirtyRegisters<Register, reg_count> _dirty{};
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@ -851,6 +852,7 @@ class MAX2837 : public MAX283x {
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reg_t read(const Register reg);
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void flush();
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Mode get_mode();
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};
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} // namespace max2837
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@ -143,6 +143,8 @@ void MAX2839::init() {
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}
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void MAX2839::set_tx_LO_iq_phase_calibration(const size_t v) {
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Mode saved_mode = get_mode();
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/* IQ phase deg CAL adj (+4 ...-4) This IC in 64 steps (6 bits), 000000 = +4deg (Q lags I by 94degs, default), 011111 = +0deg, 111111 = -4deg (Q lags I by 86degs) */
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// TX calibration , 2 x Logic pins , ENABLE, RXENABLE = 1,0, (2dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
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@ -164,7 +166,7 @@ void MAX2839::set_tx_LO_iq_phase_calibration(const size_t v) {
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_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (1 = Chip select enable )
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flush_one(Register::SPI_EN);
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set_mode(Mode::Standby); // Back 3 logic pins CALIBRATION mode -> Standby.
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set_mode(saved_mode); // restore original mode
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}
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enum class Mask {
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@ -196,11 +198,17 @@ Mask mode_mask(const Mode mode) {
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}
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void MAX2839::set_mode(const Mode mode) {
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_mode = mode;
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Mask mask = mode_mask(mode);
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gpio_max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
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gpio_max2839_rxtx.write(toUType(mask) & toUType(Mask::RxTx));
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}
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Mode MAX2839::get_mode() {
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return _mode;
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}
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void MAX2839::flush() {
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if (_dirty) {
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for (size_t n = 0; n < reg_count; n++) {
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@ -700,6 +700,7 @@ class MAX2839 : public MAX283x {
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private:
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spi::arbiter::Target& _target;
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Mode _mode{Mode::Standby};
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RegisterMap _map{initial_register_values};
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DirtyRegisters<Register, reg_count> _dirty{};
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@ -712,6 +713,7 @@ class MAX2839 : public MAX283x {
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void flush();
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void configure_rx_gain();
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Mode get_mode();
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};
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} // namespace max2839
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