mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-15 01:57:50 +00:00
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
This commit is contained in:
Maescool
@@ -98,11 +98,14 @@ typedef struct {
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uint32_t RESERVED0 : 3;
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} LPC_CGU_FREQ_MON_Type;
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typedef struct {
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__IO uint32_t ENABLE : 1;
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__IO uint32_t BYPASS : 1;
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__IO uint32_t HF : 1;
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uint32_t RESERVED0 : 29;
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typedef union {
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struct {
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__IO uint32_t ENABLE : 1;
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__IO uint32_t BYPASS : 1;
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__IO uint32_t HF : 1;
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uint32_t RESERVED0 : 29;
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};
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__IO uint32_t word;
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} LPC_CGU_XTAL_OSC_CTRL_Type;
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typedef struct {
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@@ -146,18 +149,21 @@ typedef struct {
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__IO uint32_t CLK_SEL : 5;
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uint32_t RESERVED3 : 3;
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} LPC_CGU_PLL1_CTRL_Type;
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/*
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typedef struct {
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__IO uint32_t PD : 1;
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uint32_t RESERVED0 : 1;
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__IO uint32_t IDIV : 2;
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uint32_t RESERVED1 : 7;
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__IO uint32_t AUTOBLOCK : 1;
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uint32_t RESERVED2 : 12;
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__IO uint32_t CLK_SEL : 5;
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uint32_t RESERVED3 : 3;
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typedef union {
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struct {
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__IO uint32_t PD : 1;
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uint32_t RESERVED0 : 1;
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__IO uint32_t IDIV : 2;
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uint32_t RESERVED1 : 7;
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__IO uint32_t AUTOBLOCK : 1;
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uint32_t RESERVED2 : 12;
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__IO uint32_t CLK_SEL : 5;
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uint32_t RESERVED3 : 3;
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};
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__IO uint32_t word;
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} LPC_CGU_IDIVx_CTRL_Type;
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*/
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typedef struct {
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__I uint32_t PD : 1;
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uint32_t RESERVED0 : 10;
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@@ -167,13 +173,16 @@ typedef struct {
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uint32_t RESERVED2 : 3;
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} LPC_CGU_BASE_SAFE_CLK_Type;
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typedef struct {
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__IO uint32_t PD : 1;
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uint32_t RESERVED0 : 10;
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__IO uint32_t AUTOBLOCK : 1;
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uint32_t RESERVED1 : 12;
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__IO uint32_t CLK_SEL : 5;
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uint32_t RESERVED2 : 3;
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typedef union {
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struct {
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__IO uint32_t PD : 1;
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uint32_t RESERVED0 : 10;
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__IO uint32_t AUTOBLOCK : 1;
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uint32_t RESERVED1 : 12;
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__IO uint32_t CLK_SEL : 5;
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uint32_t RESERVED2 : 3;
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};
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__IO uint32_t word;
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} LPC_CGU_BASE_CLK_Type;
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typedef struct {
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@@ -191,11 +200,11 @@ typedef struct {
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__IO uint32_t PLL0AUDIO_FRAC;
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__I uint32_t PLL1_STAT; /* +0x040 */
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__IO uint32_t PLL1_CTRL;
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__IO uint32_t IDIVA_CTRL;
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__IO uint32_t IDIVB_CTRL;
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__IO uint32_t IDIVC_CTRL; /* +0x050 */
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__IO uint32_t IDIVD_CTRL;
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__IO uint32_t IDIVE_CTRL;
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LPC_CGU_IDIVx_CTRL_Type IDIVA_CTRL;
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LPC_CGU_IDIVx_CTRL_Type IDIVB_CTRL;
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LPC_CGU_IDIVx_CTRL_Type IDIVC_CTRL; /* +0x050 */
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LPC_CGU_IDIVx_CTRL_Type IDIVD_CTRL;
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LPC_CGU_IDIVx_CTRL_Type IDIVE_CTRL;
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LPC_CGU_BASE_SAFE_CLK_Type BASE_SAFE_CLK;
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LPC_CGU_BASE_CLK_Type BASE_USB0_CLK; /* +0x060 */
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LPC_CGU_BASE_CLK_Type BASE_PERIPH_CLK;
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@@ -1065,6 +1074,47 @@ typedef struct {
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__IO uint32_t CTCR;
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} LPC_TIMER_Type;
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// ------------------------------------------------------------------------------------------------
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// ----- MOTOCONPWM -----
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// ------------------------------------------------------------------------------------------------
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/**
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* @brief Product name title=UM10503 Chapter title=LPC43xx Motor Control PWM (MOTOCONPWM) Modification date=7/26/2017 Major revision=2 Minor revision=3
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*/
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typedef struct {
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__I uint32_t CON;
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__O uint32_t CON_SET;
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__O uint32_t CON_CLR;
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__I uint32_t CAPCON;
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__O uint32_t CAPCON_SET;
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__O uint32_t CAPCON_CLR;
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__IO uint32_t TC0;
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__IO uint32_t TC1;
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__IO uint32_t TC2;
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__IO uint32_t LIM0;
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__IO uint32_t LIM1;
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__IO uint32_t LIM2;
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__IO uint32_t MAT0;
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__IO uint32_t MAT1;
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__IO uint32_t MAT2;
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__IO uint32_t DT;
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__IO uint32_t MCCP;
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__I uint32_t CAP0;
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__I uint32_t CAP1;
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__I uint32_t CAP2;
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__I uint32_t INTEN;
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__O uint32_t INTEN_SET;
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__O uint32_t INTEN_CLR;
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__I uint32_t CNTCON;
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__O uint32_t CNTCON_SET;
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__O uint32_t CNTCON_CLR;
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__I uint32_t INTF;
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__O uint32_t INTF_SET;
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__O uint32_t INTF_CLR;
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__O uint32_t CAP_CLR;
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} LPC_MCPWM_Type;
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// ------------------------------------------------------------------------------------------------
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// ----- RITIMER -----
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// ------------------------------------------------------------------------------------------------
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@@ -1409,6 +1459,7 @@ typedef struct {
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#define LPC_USART3 ((LPC_USART_Type *) LPC_USART3_BASE)
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#define LPC_TIMER2 ((LPC_TIMER_Type *) LPC_TIMER2_BASE)
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#define LPC_TIMER3 ((LPC_TIMER_Type *) LPC_TIMER3_BASE)
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#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE)
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#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
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#define LPC_I2C1 ((LPC_I2Cx_Type *) LPC_I2C1_BASE)
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#define LPC_ADC0 ((LPC_ADCx_Type *) LPC_ADC0_BASE)
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