Upstream merge to make new revision of PortaPack work (#206)

* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts
This commit is contained in:
Maescool
2019-01-11 07:56:21 +01:00
committed by Furrtek
parent bbb5dc3c12
commit 920b98f7c9
71 changed files with 9292 additions and 7067 deletions

View File

@@ -1,35 +1,15 @@
EESchema Schematic File Version 2
LIBS:portapack_h1-rescue
LIBS:hackrf_expansion
LIBS:passive
LIBS:supply
LIBS:trs_jack
LIBS:battery
LIBS:sd
LIBS:ck
LIBS:altera
LIBS:regulator
LIBS:tp
LIBS:header
LIBS:hole
LIBS:sharebrained
LIBS:fiducial
LIBS:eastrising
LIBS:on_semi
LIBS:asahi_kasei
LIBS:ti
LIBS:diode
EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 5
Sheet 4 6
Title "PortaPack H1"
Date "2017-05-22"
Rev "20170522"
Date "2018-08-20"
Rev "20180820"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2017 Jared Boone"
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
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$EndComp
$Comp
L C C34
L Device:C C34
U 1 1 53A8D5C8
P 5700 6100
F 0 "C34" H 5750 6200 50 0000 L CNN
F 1 "10U" H 5750 6000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC2012X135L45N" H 5700 6100 60 0001 C CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 5700 6100 60 0001 C CNN
F 3 "" H 5700 6100 60 0000 C CNN
F 4 "Murata" H 5700 6100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 5700 6100 60 0001 C CNN "Part"
@@ -764,7 +743,7 @@ F 5 "GRM21BR61A106KE19" H 5700 6100 60 0001 C CNN "Part"
1 0 0 -1
$EndComp
$Comp
L GND #PWR070
L power:GND #PWR070
U 1 1 53A8D5CE
P 5300 6400
F 0 "#PWR070" H 5300 6400 30 0001 C CNN
@@ -775,7 +754,7 @@ F 3 "" H 5300 6400 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR071
L power:GND #PWR071
U 1 1 53A8D5D4
P 5700 6400
F 0 "#PWR071" H 5700 6400 30 0001 C CNN
@@ -786,12 +765,12 @@ F 3 "" H 5700 6400 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L C C36
L Device:C C36
U 1 1 53A8D5DA
P 6100 7100
F 0 "C36" H 6150 7200 50 0000 L CNN
F 1 "10U" H 6150 7000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC2012X135L45N" H 6100 7100 60 0001 C CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6100 7100 60 0001 C CNN
F 3 "" H 6100 7100 60 0000 C CNN
F 4 "Murata" H 6100 7100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 6100 7100 60 0001 C CNN "Part"
@@ -799,12 +778,12 @@ F 5 "GRM21BR61A106KE19" H 6100 7100 60 0001 C CNN "Part"
1 0 0 -1
$EndComp
$Comp
L C C37
L Device:C C37
U 1 1 53A8D5E0
P 6500 7100
F 0 "C37" H 6550 7200 50 0000 L CNN
F 1 "10U" H 6550 7000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC2012X135L45N" H 6500 7100 60 0001 C CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6500 7100 60 0001 C CNN
F 3 "" H 6500 7100 60 0000 C CNN
F 4 "Murata" H 6500 7100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 6500 7100 60 0001 C CNN "Part"
@@ -812,7 +791,7 @@ F 5 "GRM21BR61A106KE19" H 6500 7100 60 0001 C CNN "Part"
1 0 0 -1
$EndComp
$Comp
L GND #PWR072
L power:GND #PWR072
U 1 1 53A8D5E6
P 6500 7400
F 0 "#PWR072" H 6500 7400 30 0001 C CNN
@@ -823,7 +802,7 @@ F 3 "" H 6500 7400 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR073
L power:GND #PWR073
U 1 1 53A8D5EC
P 6100 7400
F 0 "#PWR073" H 6100 7400 30 0001 C CNN
@@ -833,58 +812,22 @@ F 3 "" H 6100 7400 60 0000 C CNN
1 6100 7400
1 0 0 -1
$EndComp
Wire Wire Line
6500 7300 6500 7400
Wire Wire Line
6100 7300 6100 7400
Connection ~ 6100 6800
Wire Wire Line
6500 6800 6500 6900
Connection ~ 5700 6800
Wire Wire Line
6100 6800 6100 6900
Wire Wire Line
5700 6300 5700 6400
Connection ~ 5300 5800
Wire Wire Line
5700 5800 5700 5900
Wire Wire Line
5300 6300 5300 6400
Connection ~ 4900 5800
Wire Wire Line
5300 5800 5300 5900
Connection ~ 5300 6800
Wire Wire Line
5300 6800 5300 6900
Connection ~ 4900 6800
Wire Wire Line
5300 7300 5300 7400
Wire Wire Line
5700 7300 5700 7400
Wire Wire Line
5700 6800 5700 6900
Connection ~ 4500 6800
Wire Wire Line
4900 6800 4900 6900
4500 6800 4900 6800
Wire Wire Line
4500 6800 6500 6800
Wire Wire Line
4500 6700 4500 6900
4500 6700 4500 6800
Connection ~ 4500 5800
Wire Wire Line
4900 5800 4900 5900
4500 5800 4900 5800
Wire Wire Line
4500 5800 6500 5800
Wire Wire Line
4500 5700 4500 5900
Wire Wire Line
4500 6300 4500 6400
Wire Wire Line
4900 6300 4900 6400
Wire Wire Line
4500 7300 4500 7400
Wire Wire Line
4900 7300 4900 7400
4500 5700 4500 5800
Wire Wire Line
9100 5500 9100 4650
Text Label 3900 2600 0 60 ~ 0
@@ -916,8 +859,6 @@ Wire Wire Line
Wire Wire Line
1900 5300 1800 5300
Connection ~ 1900 5100
Wire Bus Line
7600 650 10750 650
Entry Wire Line
8200 650 8300 750
Entry Wire Line
@@ -1022,19 +963,17 @@ Text HLabel 1800 5300 0 60 Input ~ 0
I2S0_RX_SDA
Text Label 10150 3700 0 60 ~ 0
P2_8
Wire Bus Line
10750 650 10750 2700
Wire Wire Line
10050 3300 10300 3300
Wire Wire Line
10300 3400 10050 3400
$Comp
L C C42
L Device:C C42
U 1 1 53B1911F
P 6100 6100
F 0 "C42" H 6150 6200 50 0000 L CNN
F 1 "10U" H 6150 6000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC2012X135L45N" H 6100 6100 60 0001 C CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6100 6100 60 0001 C CNN
F 3 "" H 6100 6100 60 0000 C CNN
F 4 "Murata" H 6100 6100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 6100 6100 60 0001 C CNN "Part"
@@ -1042,7 +981,7 @@ F 5 "GRM21BR61A106KE19" H 6100 6100 60 0001 C CNN "Part"
1 0 0 -1
$EndComp
$Comp
L GND #PWR074
L power:GND #PWR074
U 1 1 53B1912C
P 6100 6400
F 0 "#PWR074" H 6100 6400 30 0001 C CNN
@@ -1052,18 +991,14 @@ F 3 "" H 6100 6400 60 0000 C CNN
1 6100 6400
1 0 0 -1
$EndComp
Wire Wire Line
6100 6300 6100 6400
Wire Wire Line
6100 5800 6100 5900
Connection ~ 5700 5800
$Comp
L C C43
L Device:C C43
U 1 1 53B1A065
P 6500 6100
F 0 "C43" H 6550 6200 50 0000 L CNN
F 1 "10U" H 6550 6000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC2012X135L45N" H 6500 6100 60 0001 C CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6500 6100 60 0001 C CNN
F 3 "" H 6500 6100 60 0000 C CNN
F 4 "Murata" H 6500 6100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 6500 6100 60 0001 C CNN "Part"
@@ -1071,7 +1006,7 @@ F 5 "GRM21BR61A106KE19" H 6500 6100 60 0001 C CNN "Part"
1 0 0 -1
$EndComp
$Comp
L GND #PWR075
L power:GND #PWR075
U 1 1 53B1A072
P 6500 6400
F 0 "#PWR075" H 6500 6400 30 0001 C CNN
@@ -1081,11 +1016,7 @@ F 3 "" H 6500 6400 60 0000 C CNN
1 6500 6400
1 0 0 -1
$EndComp
Wire Wire Line
6500 5800 6500 5900
Connection ~ 6100 5800
Wire Wire Line
6500 6300 6500 6400
Wire Wire Line
6850 2600 6100 2600
Wire Wire Line
@@ -1128,7 +1059,6 @@ Entry Wire Line
10650 2300 10750 2200
Wire Wire Line
7600 1050 7800 1050
NoConn ~ 10050 3600
Text HLabel 6100 2600 0 60 Output ~ 0
AUDIO_RESET#
Text HLabel 3700 1800 2 60 Input ~ 0
@@ -1143,7 +1073,6 @@ Text Notes 4500 1900 0 60 ~ 0
Init: I/O is hi-Z with pull-ups.\nSRAM download when VCCINT reaches 1V55.\nUser mode once downloaded and VCCIO OK.\nVCCINT stable to user mode: 200 usec max.\nVCCIOs stable to user mode: 2 usec.\n\nPull-ups: 5-25k @ 3V3, 25-60k @ 1V8.\nExternal R-pull: 1K PD, 10K PU recommended.\nVCCIO=3V3: 2V5, 3V3 inputs OK.\nVCCIO=1V8: 1V5, 1V8, 2V5, 3V3 inputs OK.\n\nJTAG active w/VCCINT, but refers to VCCIO.\nTDI, TMS: weak internal PU\nTCK: weak internal PD (keep low at power-up)
Wire Wire Line
10700 3700 10050 3700
NoConn ~ 10050 3500
Entry Wire Line
8100 650 8200 750
Wire Wire Line
@@ -1152,10 +1081,8 @@ Wire Wire Line
11050 2900 10050 2900
Wire Wire Line
11050 3100 10050 3100
NoConn ~ 6850 2700
NoConn ~ 6850 2900
$Comp
L GND #PWR076
L power:GND #PWR076
U 1 1 58FC4CC1
P 7800 1050
F 0 "#PWR076" H 7800 1050 30 0001 C CNN
@@ -1165,5 +1092,95 @@ F 3 "" H 7800 1050 60 0000 C CNN
1 7800 1050
0 -1 -1 0
$EndComp
NoConn ~ 3600 2400
Wire Wire Line
6100 6800 6500 6800
Wire Wire Line
5700 6800 6100 6800
Wire Wire Line
5300 5800 5700 5800
Wire Wire Line
4900 5800 5300 5800
Wire Wire Line
5300 6800 5700 6800
Wire Wire Line
4900 6800 5300 6800
Wire Wire Line
1900 5100 2000 5100
Wire Wire Line
5700 5800 6100 5800
Wire Wire Line
6100 5800 6500 5800
Wire Wire Line
4500 5800 4500 5950
Wire Wire Line
4500 6250 4500 6400
Wire Wire Line
4900 6250 4900 6400
Wire Wire Line
4900 5800 4900 5950
Wire Wire Line
5300 5800 5300 5950
Wire Wire Line
5300 6250 5300 6400
Wire Wire Line
5700 6250 5700 6400
Wire Wire Line
5700 5800 5700 5950
Wire Wire Line
6100 5800 6100 5950
Wire Wire Line
6100 6250 6100 6400
Wire Wire Line
6500 6250 6500 6400
Wire Wire Line
6500 5800 6500 5950
Wire Wire Line
4500 6800 4500 6950
Wire Wire Line
4500 7250 4500 7400
Wire Wire Line
4900 7250 4900 7400
Wire Wire Line
4900 6800 4900 6950
Wire Wire Line
5300 6800 5300 6950
Wire Wire Line
5300 7250 5300 7400
Wire Wire Line
5700 7250 5700 7400
Wire Wire Line
5700 6800 5700 6950
Wire Wire Line
6100 6800 6100 6950
Wire Wire Line
6100 7250 6100 7400
Wire Wire Line
6500 7250 6500 7400
Wire Wire Line
6500 6800 6500 6950
Wire Wire Line
3800 2400 3600 2400
Text HLabel 3800 2400 2 60 BiDi ~ 0
CLKIN
Text HLabel 6100 2700 0 60 Output ~ 0
REF_EN
Wire Wire Line
6100 2700 6850 2700
NoConn ~ 2000 2400
Text HLabel 10300 3500 2 60 Input ~ 0
GPS_TX_READY
Wire Wire Line
10300 3500 10050 3500
Text HLabel 10300 3600 2 60 Input ~ 0
GPS_TIMEPULSE
Wire Wire Line
10050 3600 10300 3600
Text HLabel 6100 2900 0 60 Output ~ 0
GPS_RESET#
Wire Wire Line
6100 2900 6850 2900
Wire Bus Line
10750 650 10750 2700
Wire Bus Line
7600 650 10750 650
$EndSCHEMATC