Upstream merge to make new revision of PortaPack work (#206)

* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts

hardware/portapack_h1/portapack_h1.sch

@@ -1,41 +1,21 @@
-EESchema Schematic File Version 2
-LIBS:portapack_h1-rescue
-LIBS:hackrf_expansion
-LIBS:passive
-LIBS:supply
-LIBS:trs_jack
-LIBS:battery
-LIBS:sd
-LIBS:ck
-LIBS:altera
-LIBS:regulator
-LIBS:tp
-LIBS:header
-LIBS:hole
-LIBS:sharebrained
-LIBS:fiducial
-LIBS:eastrising
-LIBS:on_semi
-LIBS:asahi_kasei
-LIBS:ti
-LIBS:diode
+EESchema Schematic File Version 4
 LIBS:portapack_h1-cache
-EELAYER 25 0
+EELAYER 26 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 1 5
+Sheet 1 6
 Title "PortaPack H1"
-Date "2017-05-22"
-Rev "20170522"
+Date "2018-08-20"
+Rev "20180820"
 Comp "ShareBrained Technology, Inc."
-Comment1 "Copyright © 2014-2017 Jared Boone"
+Comment1 "Copyright © 2014-2018 Jared Boone"
 Comment2 "License: GNU General Public License, version 2"
 Comment3 ""
 Comment4 ""
 $EndDescr
 $Comp
-L HOLE1 H2
+L hole:HOLE1 H2
 U 1 1 5369BBD8
 P 9500 1900
 F 0 "H2" H 9500 2050 60  0000 C CNN
@@ -46,7 +26,7 @@ F 3 "" H 9500 1900 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L HOLE1 H3
+L hole:HOLE1 H3
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 F 0 "H3" H 9500 2550 60  0000 C CNN
@@ -57,7 +37,7 @@ F 3 "" H 9500 2400 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L HOLE1 H4
+L hole:HOLE1 H4
 U 1 1 5369BC00
 P 9500 2900
 F 0 "H4" H 9500 3050 60  0000 C CNN
@@ -68,7 +48,7 @@ F 3 "" H 9500 2900 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L HOLE1 H5
+L hole:HOLE1 H5
 U 1 1 5369BC14
 P 9500 3400
 F 0 "H5" H 9500 3550 60  0000 C CNN
@@ -180,6 +160,11 @@ F36 "VIN" I R 6600 5200 60
 F37 "VBUS" O R 6600 5000 60 
 F38 "VBUSCTRL" I R 6600 5100 60 
 F39 "VBAT" I L 4700 5200 60 
+F40 "CLKIN" B L 4700 4900 60 
+F41 "REF_EN" O L 4700 5000 60 
+F42 "GPS_TX_READY" I L 4700 2800 60 
+F43 "GPS_TIMEPULSE" I L 4700 2900 60 
+F44 "GPS_RESET#" O L 4700 3000 60 
 $EndSheet
 Wire Wire Line
 	6600 1900 7600 1900
@@ -240,15 +225,15 @@ Wire Wire Line
 Wire Wire Line
 	3700 2300 4700 2300
 Wire Wire Line
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+	4700 2500 4000 2500
 Wire Wire Line
-	3700 2600 4700 2600
+	3700 2600 4100 2600
 Wire Wire Line
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+	9800 1900 9800 2400
 Connection ~ 9800 2400
 Connection ~ 9800 2900
 $Comp
-L FIDUCIAL FID1
+L fiducial:FIDUCIAL FID1
 U 1 1 53B309AC
 P 4100 7100
 F 0 "FID1" H 4100 7225 60  0000 C CNN
@@ -259,7 +244,7 @@ F 3 "" H 4100 7100 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L FIDUCIAL FID2
+L fiducial:FIDUCIAL FID2
 U 1 1 53B30B4C
 P 4100 7500
 F 0 "FID2" H 4100 7625 60  0000 C CNN
@@ -270,7 +255,7 @@ F 3 "" H 4100 7500 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L FIDUCIAL FID3
+L fiducial:FIDUCIAL FID3
 U 1 1 53B30CEC
 P 4700 7100
 F 0 "FID3" H 4700 7225 60  0000 C CNN
@@ -281,18 +266,7 @@ F 3 "" H 4700 7100 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L FIDUCIAL FID4
-U 1 1 53B30E8C
-P 4700 7500
-F 0 "FID4" H 4700 7625 60  0000 C CNN
-F 1 "FIDUCIAL" H 4700 7375 60  0000 C CNN
-F 2 "fiducial:FIDUCIAL_65MIL" H 4700 7500 60  0001 C CNN
-F 3 "" H 4700 7500 60  0000 C CNN
-	1    4700 7500
-	1    0    0    -1  
-$EndComp
-$Comp
-L GND #PWR01
+L power:GND #PWR01
 U 1 1 53B3303D
 P 9800 3500
 F 0 "#PWR01" H 9800 3500 30  0001 C CNN
@@ -310,7 +284,7 @@ Wire Wire Line
 Wire Wire Line
 	4700 1700 3700 1700
 $Sheet
-S 4700 5600 1900 700 
+S 4700 5600 1900 1000
 U 58CFF3E3
 F0 "power" 50
 F1 "power.sch" 50
@@ -323,6 +297,9 @@ F7 "VBUS" I R 6600 5700 60
 F8 "VBUSCTRL" O R 6600 5800 60 
 F9 "VIN" O R 6600 5900 60 
 F10 "VBAT" O L 4700 5700 60 
+F11 "REF_CLK" O L 4700 6500 60 
+F12 "REF_EN" I L 4700 6400 60 
+F13 "GPS_VCC" O R 6600 6400 60 
 $EndSheet
 Wire Wire Line
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 Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Sheet
+S 4700 600  1900 800 
+U 5B7E0B2A
+F0 "gps" 50
+F1 "gps.sch" 50
+F2 "SDA" B L 4700 800 60 
+F3 "SCL" B L 4700 700 60 
+F4 "V_BACKUP" I L 4700 1300 60 
+F5 "VCC" I R 6600 1300 60 
+F6 "TIMEPULSE" O L 4700 1000 60 
+F7 "RESET#" I L 4700 1100 60 
+F8 "TX_READY" O L 4700 900 60 
+$EndSheet
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4000 2500
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4100 2600
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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 $EndSCHEMATC