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C++14: make some wrapper classes static.

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Also address GCC 6.2 not allowing constexpr from reinterpret_cast<> values.
This commit is contained in:
Jared Boone 2017-01-05 17:10:00 -08:00
parent 0ea2f9650e
commit a22dc150bc
5 changed files with 68 additions and 69 deletions
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10
firmware/application/touch_adc.cpp
View File

@ -57,14 +57,14 @@ constexpr lpc43xx::adc::Config adc0_config {
}; };
void init() { void init() {
adc0.clock_enable(); adc0::clock_enable();
adc0.interrupts_disable(); adc0::interrupts_disable();
adc0.power_up(adc0_config); adc0::power_up(adc0_config);
adc0.interrupts_enable(adc0_interrupt_mask); adc0::interrupts_enable(adc0_interrupt_mask);
} }
void start() { void start() {
adc0.start_burst(); adc0::start_burst();
} }
// static constexpr bool monitor_overruns_and_not_dones = false; // static constexpr bool monitor_overruns_and_not_dones = false;

12
firmware/baseband/rssi.cpp
View File

@ -52,22 +52,22 @@ constexpr adc::Config adc1_config {
}; };
void init() { void init() {
adc1.clock_enable(); adc1::clock_enable();
adc1.interrupts_disable(); adc1::interrupts_disable();
adc1.power_up(adc1_config); adc1::power_up(adc1_config);
adc1.interrupts_enable(adc1_interrupt_mask); adc1::interrupts_enable(adc1_interrupt_mask);
dma::init(); dma::init();
} }
void start() { void start() {
dma::enable(); dma::enable();
adc1.start_burst(); adc1::start_burst();
} }
void stop() { void stop() {
dma::disable(); dma::disable();
adc1.stop_burst(); adc1::stop_burst();
} }
} /* namespace rssi */ } /* namespace rssi */

65
firmware/common/adc.hpp
View File

@ -52,84 +52,81 @@ struct Config {
uint32_t cr; uint32_t cr;
}; };
template<uint32_t BaseAddress>
class ADC { class ADC {
public: public:
constexpr ADC( static void power_up(const Config config) {
LPC_ADCx_Type* adcp adcp().CR = config.cr;
) : adcp(adcp)
{
} }
void power_up(const Config config) const { static void clock_enable() {
adcp->CR = config.cr; if( &adcp() == LPC_ADC0 ) {
}
void clock_enable() const {
if( adcp == LPC_ADC0 ) {
LPC_CCU1->CLK_APB3_ADC0_CFG.AUTO = 1; LPC_CCU1->CLK_APB3_ADC0_CFG.AUTO = 1;
LPC_CCU1->CLK_APB3_ADC0_CFG.RUN = 1; LPC_CCU1->CLK_APB3_ADC0_CFG.RUN = 1;
} }
if( adcp == LPC_ADC1 ) { if( &adcp() == LPC_ADC1 ) {
LPC_CCU1->CLK_APB3_ADC1_CFG.AUTO = 1; LPC_CCU1->CLK_APB3_ADC1_CFG.AUTO = 1;
LPC_CCU1->CLK_APB3_ADC1_CFG.RUN = 1; LPC_CCU1->CLK_APB3_ADC1_CFG.RUN = 1;
} }
} }
void clock_disable() const { static void clock_disable() {
if( adcp == LPC_ADC0 ) { if( &adcp() == LPC_ADC0 ) {
LPC_CCU1->CLK_APB3_ADC0_CFG.RUN = 0; LPC_CCU1->CLK_APB3_ADC0_CFG.RUN = 0;
} }
if( adcp == LPC_ADC1 ) { if( &adcp() == LPC_ADC1 ) {
LPC_CCU1->CLK_APB3_ADC1_CFG.RUN = 0; LPC_CCU1->CLK_APB3_ADC1_CFG.RUN = 0;
} }
} }
void disable() const { static void disable() {
adcp->INTEN = 0; adcp().INTEN = 0;
adcp->CR = 0; adcp().CR = 0;
clock_disable(); clock_disable();
} }
void interrupts_disable() const { static void interrupts_disable() {
adcp->INTEN = 0; adcp().INTEN = 0;
} }
void interrupts_enable(const uint32_t mask) const { static void interrupts_enable(const uint32_t mask) {
adcp->INTEN = mask; adcp().INTEN = mask;
} }
void start_burst() const { static void start_burst() {
adcp->CR |= (1U << 16); adcp().CR |= (1U << 16);
} }
void start_once() const { static void start_once() {
adcp->CR |= (1U << 24); adcp().CR |= (1U << 24);
} }
void start_once(size_t n) const { static void start_once(size_t n) {
uint32_t cr = adcp->CR; uint32_t cr = adcp().CR;
cr &= ~(0xffU); cr &= ~(0xffU);
cr |= (1 << 24) | (1 << n); cr |= (1 << 24) | (1 << n);
adcp->CR = cr; adcp().CR = cr;
} }
void stop_burst() const { static void stop_burst() {
adcp->CR &= ~(1U << 16); adcp().CR &= ~(1U << 16);
} }
uint32_t convert(size_t n) const { static uint32_t convert(size_t n) {
start_once(n); start_once(n);
while(true) { while(true) {
const uint32_t data = adcp->DR[n]; const uint32_t data = adcp().DR[n];
if( (data >> 31) & 1 ) { if( (data >> 31) & 1 ) {
return (data >> 6) & 0x3ff; return (data >> 6) & 0x3ff;
} }
} }
} }
private: private:
LPC_ADCx_Type* const adcp; static LPC_ADCx_Type& adcp() {
return *reinterpret_cast<LPC_ADCx_Type*>(BaseAddress);
}
}; };
} /* namespace adc */ } /* namespace adc */

4
firmware/common/hackrf_hal.hpp
View File

@ -67,11 +67,11 @@ constexpr size_t clock_generator_output_mcu_clkin = 7;
/* ADC0 */ /* ADC0 */
constexpr adc::ADC adc0 { LPC_ADC0 }; using adc0 = adc::ADC<LPC_ADC0_BASE>;
/* ADC1 */ /* ADC1 */
constexpr adc::ADC adc1 { LPC_ADC1 }; using adc1 = adc::ADC<LPC_ADC1_BASE>;
void reset(); void reset();

46
firmware/common/i2s.hpp
View File

@ -155,8 +155,6 @@ struct ConfigDMA {
template<uint32_t BaseAddress> template<uint32_t BaseAddress>
class I2S { class I2S {
public: public:
static constexpr LPC_I2S_Type* Peripheral = reinterpret_cast<LPC_I2S_Type*>(BaseAddress);
static void configure( static void configure(
const ConfigTX& config_tx, const ConfigTX& config_tx,
const ConfigRX& config_rx const ConfigRX& config_rx
@ -167,28 +165,28 @@ public:
/* NOTE: Documentation of CREG6 is quite confusing. Refer to "I2S clocking and /* NOTE: Documentation of CREG6 is quite confusing. Refer to "I2S clocking and
* pin connections" and other I2S diagrams for more clarity. * pin connections" and other I2S diagrams for more clarity.
*/ */
if( Peripheral == LPC_I2S0 ) { if( &p() == LPC_I2S0 ) {
LPC_CREG->CREG6 |= LPC_CREG->CREG6 |=
(1U << 12) (1U << 12)
| (1U << 13) | (1U << 13)
; ;
} }
if( Peripheral == LPC_I2S1 ) { if( &p() == LPC_I2S1 ) {
LPC_CREG->CREG6 |= LPC_CREG->CREG6 |=
(1U << 14) (1U << 14)
| (1U << 15) | (1U << 15)
; ;
} }
Peripheral->DAO = config_tx.dao; p().DAO = config_tx.dao;
Peripheral->TXRATE = config_tx.txrate; p().TXRATE = config_tx.txrate;
Peripheral->TXBITRATE = config_tx.txbitrate; p().TXBITRATE = config_tx.txbitrate;
Peripheral->TXMODE = config_tx.txmode; p().TXMODE = config_tx.txmode;
Peripheral->DAI = config_rx.dai; p().DAI = config_rx.dai;
Peripheral->RXRATE = config_rx.rxrate; p().RXRATE = config_rx.rxrate;
Peripheral->RXBITRATE = config_rx.rxbitrate; p().RXBITRATE = config_rx.rxbitrate;
Peripheral->RXMODE = config_rx.rxmode; p().RXMODE = config_rx.rxmode;
} }
static void configure( static void configure(
@ -198,38 +196,42 @@ public:
) { ) {
configure(config_tx, config_rx); configure(config_tx, config_rx);
Peripheral->DMA1 = config_dma.dma1; p().DMA1 = config_dma.dma1;
Peripheral->DMA2 = config_dma.dma2; p().DMA2 = config_dma.dma2;
} }
static void rx_start() { static void rx_start() {
Peripheral->DAI &= ~(1U << 3); p().DAI &= ~(1U << 3);
} }
static void rx_stop() { static void rx_stop() {
Peripheral->DAI |= (1U << 3); p().DAI |= (1U << 3);
} }
static void tx_start() { static void tx_start() {
Peripheral->DAO &= ~(1U << 3); p().DAO &= ~(1U << 3);
} }
static void tx_stop() { static void tx_stop() {
Peripheral->DAO |= (1U << 3); p().DAO |= (1U << 3);
} }
static void tx_mute() { static void tx_mute() {
Peripheral->DAO |= (1U << 15); p().DAO |= (1U << 15);
} }
static void tx_unmute() { static void tx_unmute() {
Peripheral->DAO &= ~(1U << 15); p().DAO &= ~(1U << 15);
} }
private: private:
static void reset() { static void reset() {
Peripheral->DAO |= (1U << 4); p().DAO |= (1U << 4);
Peripheral->DAI |= (1U << 4); p().DAI |= (1U << 4);
}
static LPC_I2S_Type& p() {
return *reinterpret_cast<LPC_I2S_Type*>(BaseAddress);
} }
}; };