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https://github.com/portapack-mayhem/mayhem-firmware.git
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H4M CPLD (#2335)
* Added CPLD code for H4M * Added CPLD code for H4M * Added CPLD code for H4M * Added CPLD code for H4M * Clean up * Clean up
This commit is contained in:
jLynx
GitHub
parent
d6a9c74665
commit
abd6177303
14
hardware/portapack_h4m/CPLD/.gitignore
vendored
Normal file
14
hardware/portapack_h4m/CPLD/.gitignore
vendored
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**/*.qws
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**/*.chg
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**/smart.log
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**/db/
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**/incremental_db/
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**/output_files/*.done
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**/output_files/*.smsg
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**/output_files/*.summary
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**/output_files/*.jdi
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**/output_files/*.pin
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**/output_files/*.pof
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**/output_files/*.rpt
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**/output_files/*.sld
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**/simulation/
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109
hardware/portapack_h4m/CPLD/AG256SL100/Makefile
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109
hardware/portapack_h4m/CPLD/AG256SL100/Makefile
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#
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# Copyright (C) 2017 Jared Boone, ShareBrained Technology, Inc.
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# Copyright (C) 2024 jLynx.net https://github.com/jLynx
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#
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# This file is part of PortaPack.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; see the file COPYING. If not, write to
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# the Free Software Foundation, Inc., 51 Franklin Street,
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# Boston, MA 02110-1301, USA.
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# Makefile based on Altera Quartus documentation example, topic
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# "About Using Quartus II from the Command Line"
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###################################################################
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# Project Configuration:
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#
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# Specify the name of the design (project) and Quartus II Settings
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# File (.qsf) and the list of source files used.
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###################################################################
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PROJECT=portapack_h4m_cpld
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SOURCE_FILES=top.vhd
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ASSIGNMENT_FILES=$(PROJECT).qpf $(PROJECT).qsf $(PROJECT).sdc
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OUTPUT_DIR=output_files
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and database
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###################################################################
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all: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt $(OUTPUT_DIR)/$(PROJECT).sta.rpt
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clean:
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rm -rf *.chg *.qws smart.log db/ incremental_db/ $(OUTPUT_DIR)/
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map: smart.log $(OUTPUT_DIR)/$(PROJECT).map.rpt
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fit: smart.log $(OUTPUT_DIR)/$(PROJECT).fit.rpt
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asm: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt
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sta: smart.log $(OUTPUT_DIR)/$(PROJECT).sta.rpt
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smart: smart.log
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###################################################################
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# Executable Configuration
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###################################################################
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MAP_ARGS=
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FIT_ARGS=
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ASM_ARGS=
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STA_ARGS=
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###################################################################
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# Target implementations
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###################################################################
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STAMP = echo done >
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$(OUTPUT_DIR)/$(PROJECT).map.rpt: $(SOURCE_FILES)
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quartus_map $(MAP_ARGS) $(PROJECT)
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$(STAMP) fit.chg
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$(OUTPUT_DIR)/$(PROJECT).fit.rpt: fit.chg $(OUTPUT_DIR)/$(PROJECT).map.rpt
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quartus_fit $(FIT_ARGS) $(PROJECT)
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$(STAMP) asm.chg
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$(STAMP) sta.chg
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$(OUTPUT_DIR)/$(PROJECT).asm.rpt: asm.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
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quartus_asm $(ASM_ARGS) $(PROJECT)
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$(OUTPUT_DIR)/$(PROJECT).sta.rpt: sta.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
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quartus_sta $(STA_ARGS) $(PROJECT)
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smart.log: $(ASSIGNMENT_FILES) $(OUTPUT_DIR)
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quartus_sh --determine_smart_action $(PROJECT) > smart.log
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###################################################################
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# Project initialization
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###################################################################
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$(OUTPUT_DIR):
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mkdir $(OUTPUT_DIR)
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$(ASSIGNMENT_FILES): $(OUTPUT_DIR)
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quartus_sh --prepare $(PROJECT)
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fit.chg:
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$(STAMP) fit.chg
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sta.chg:
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$(STAMP) sta.chg
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asm.chg:
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$(STAMP) asm.chg
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File diff suppressed because it is too large
Load Diff
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
|
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# functions, and any output files from any of the foregoing
|
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# (including device programming or simulation files), and any
|
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
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# Agreement, or other applicable license agreement, including,
|
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
|
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 21:24:55 April 29, 2014
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "13.1"
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DATE = "21:24:55 April 29, 2014"
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# Revisions
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PROJECT_REVISION = "portapack_h4m_cpld"
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352
hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qsf
Normal file
352
hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qsf
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@ -0,0 +1,352 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation
|
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# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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||||
# Date created = 21:24:55 April 29, 2014
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# portapack_h4m_cpld_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX II"
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set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
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set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL
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set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[15]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[14]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[13]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[12]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[11]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[10]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[9]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[8]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[6]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RDX
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RS
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_TE
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_WRX
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
|
||||
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
|
||||
set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
|
||||
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
|
||||
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h2/cpld -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name GENERATE_RBF_FILE OFF
|
||||
set_global_assignment -name GENERATE_SVF_FILE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RESETX
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF
|
||||
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
|
||||
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
|
||||
set_instance_assignment -name PCI_IO OFF -to MCU_DIR
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to AUDIO_RESETX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RDX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WRX
|
||||
set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WRX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_TE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_P2_8
|
||||
set_instance_assignment -name PCI_IO OFF -to MCU_P2_8
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[15]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[14]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[13]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[12]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[11]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[10]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[9]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[8]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_ADDR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_DIR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_IO_STBX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_RDX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MCU_LCD_WRX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MCU_P2_8
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name PCI_IO OFF -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TIMEPULSE
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TX_READY
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TX_READY
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TX_READY
|
||||
set_instance_assignment -name PCI_IO OFF -to GPS_TX_READY
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TX_READY
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to REF_EN
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to REF_EN
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to REF_EN
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_RESETX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_RESETX
|
||||
|
||||
set_location_assignment PIN_58 -to REF_EN
|
||||
set_location_assignment PIN_72 -to MCU_DIR
|
||||
set_location_assignment PIN_41 -to MCU_IO_STBX
|
||||
set_location_assignment PIN_40 -to MCU_LCD_TE
|
||||
set_location_assignment PIN_43 -to MCU_P2_8
|
||||
set_location_assignment PIN_71 -to MCU_LCD_WRX
|
||||
set_location_assignment PIN_42 -to MCU_ADDR
|
||||
set_location_assignment PIN_39 -to MCU_LCD_RDX
|
||||
set_location_assignment PIN_35 -to MCU_D[0]
|
||||
set_location_assignment PIN_33 -to MCU_D[2]
|
||||
set_location_assignment PIN_28 -to MCU_D[4]
|
||||
set_location_assignment PIN_27 -to MCU_D[6]
|
||||
set_location_assignment PIN_8 -to TP_U
|
||||
set_location_assignment PIN_7 -to TP_L
|
||||
set_location_assignment PIN_6 -to TP_D
|
||||
set_location_assignment PIN_5 -to TP_R
|
||||
set_location_assignment PIN_26 -to MCU_D[7]
|
||||
set_location_assignment PIN_29 -to MCU_D[5]
|
||||
set_location_assignment PIN_30 -to MCU_D[3]
|
||||
set_location_assignment PIN_36 -to MCU_D[1]
|
||||
set_location_assignment PIN_73 -to GPS_RESETX
|
||||
set_location_assignment PIN_75 -to GPS_TX_READY
|
||||
set_location_assignment PIN_74 -to GPS_TIMEPULSE
|
||||
set_location_assignment PIN_34 -to SW_U
|
||||
set_location_assignment PIN_37 -to SW_L
|
||||
set_location_assignment PIN_17 -to SW_SEL
|
||||
set_location_assignment PIN_12 -to SW_R
|
||||
set_location_assignment PIN_14 -to SW_D
|
||||
set_location_assignment PIN_15 -to SW_ROT_A
|
||||
set_location_assignment PIN_16 -to SW_ROT_B
|
||||
set_location_assignment PIN_99 -to LCD_DB[0]
|
||||
set_location_assignment PIN_98 -to LCD_DB[1]
|
||||
set_location_assignment PIN_97 -to LCD_DB[2]
|
||||
set_location_assignment PIN_96 -to LCD_DB[3]
|
||||
set_location_assignment PIN_95 -to LCD_DB[4]
|
||||
set_location_assignment PIN_92 -to LCD_DB[5]
|
||||
set_location_assignment PIN_91 -to LCD_DB[6]
|
||||
set_location_assignment PIN_90 -to LCD_DB[7]
|
||||
set_location_assignment PIN_89 -to LCD_DB[8]
|
||||
set_location_assignment PIN_88 -to LCD_DB[9]
|
||||
set_location_assignment PIN_87 -to LCD_DB[10]
|
||||
set_location_assignment PIN_86 -to LCD_DB[11]
|
||||
set_location_assignment PIN_85 -to LCD_DB[12]
|
||||
set_location_assignment PIN_84 -to LCD_DB[13]
|
||||
set_location_assignment PIN_83 -to LCD_DB[14]
|
||||
set_location_assignment PIN_82 -to LCD_DB[15]
|
||||
set_location_assignment PIN_100 -to LCD_RESETX
|
||||
set_location_assignment PIN_1 -to LCD_RDX
|
||||
set_location_assignment PIN_3 -to LCD_RS
|
||||
set_location_assignment PIN_2 -to LCD_WRX
|
||||
set_location_assignment PIN_76 -to LCD_BACKLIGHT
|
||||
set_location_assignment PIN_4 -to LCD_TE
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_location_assignment PIN_38 -to DEVICE_RESET_V
|
||||
set_location_assignment PIN_44 -to DEVICE_RESET
|
||||
set_global_assignment -name SDC_FILE portapack_h4m_cpld.sdc
|
||||
set_global_assignment -name VHDL_FILE top.vhd
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SYSOFF
|
||||
set_location_assignment PIN_47 -to SYSOFF
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SYSOFF
|
||||
116
hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc
Normal file
116
hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc
Normal file
@ -0,0 +1,116 @@
|
||||
## Generated SDC file "portapack_hackrf_one_cpld.sdc"
|
||||
|
||||
## Copyright (C) 1991-2014 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
|
||||
|
||||
## DATE "Sat May 3 10:22:18 2014"
|
||||
|
||||
##
|
||||
## DEVICE "5M40ZE64C5"
|
||||
##
|
||||
|
||||
# RS = 0, D = DB[15:8]
|
||||
# wait max(tast = 0 ns, CPLD setup = ?)
|
||||
# WR = 0, D = DB[7:0]
|
||||
# wait max(CPLD )
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
set mcu_clk_period 4.9
|
||||
|
||||
set lcd_data_wr_setup 10.0
|
||||
set lcd_data_wr_hold 10.0
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {MCU_LCD_WRX} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WRX}]
|
||||
#create_clock -name strobe_virt -period 66.000
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_input_delay -clock strobe_virt [get_ports {D[*]}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}]
|
||||
#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@ -0,0 +1 @@
|
||||
dft_skip_oct_vccn_check = on
|
||||
207
hardware/portapack_h4m/CPLD/AG256SL100/top.vhd
Normal file
207
hardware/portapack_h4m/CPLD/AG256SL100/top.vhd
Normal file
@ -0,0 +1,207 @@
|
||||
--
|
||||
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
|
||||
-- Copyright (C) 2024 jLynx.net https://github.com/jLynx
|
||||
--
|
||||
-- This file is part of PortaPack.
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2, or (at your option)
|
||||
-- any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; see the file COPYING. If not, write to
|
||||
-- the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
-- Boston, MA 02110-1301, USA.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity top is
|
||||
port (
|
||||
MCU_D : inout std_logic_vector(7 downto 0);
|
||||
MCU_DIR : in std_logic;
|
||||
MCU_IO_STBX : in std_logic;
|
||||
MCU_LCD_WRX : in std_logic;
|
||||
MCU_ADDR : in std_logic;
|
||||
MCU_LCD_TE : out std_logic;
|
||||
MCU_P2_8 : in std_logic;
|
||||
MCU_LCD_RDX : in std_logic;
|
||||
|
||||
TP_U : out std_logic;
|
||||
TP_D : out std_logic;
|
||||
TP_L : out std_logic;
|
||||
TP_R : out std_logic;
|
||||
|
||||
SW_SEL : in std_logic;
|
||||
SW_ROT_A : in std_logic;
|
||||
SW_ROT_B : in std_logic;
|
||||
SW_U : in std_logic;
|
||||
SW_D : in std_logic;
|
||||
SW_L : in std_logic;
|
||||
SW_R : in std_logic;
|
||||
|
||||
LCD_RESETX : out std_logic;
|
||||
LCD_RS : out std_logic;
|
||||
LCD_WRX : out std_logic;
|
||||
LCD_RDX : out std_logic;
|
||||
LCD_DB : inout std_logic_vector(15 downto 0);
|
||||
LCD_TE : in std_logic;
|
||||
LCD_BACKLIGHT : out std_logic;
|
||||
|
||||
SYSOFF : out std_logic;
|
||||
|
||||
AUDIO_RESETX : out std_logic;
|
||||
|
||||
REF_EN : out std_logic;
|
||||
|
||||
GPS_RESETX : out std_logic;
|
||||
GPS_TX_READY : in std_logic;
|
||||
GPS_TIMEPULSE : in std_logic;
|
||||
|
||||
DEVICE_RESET : in std_logic;
|
||||
DEVICE_RESET_V : in std_logic
|
||||
);
|
||||
end top;
|
||||
|
||||
architecture rtl of top is
|
||||
|
||||
signal switches : std_logic_vector(7 downto 0);
|
||||
|
||||
type data_direction_t is (from_mcu, to_mcu);
|
||||
signal data_dir : data_direction_t;
|
||||
|
||||
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
|
||||
signal mcu_data_out_io : std_logic_vector(7 downto 0);
|
||||
signal mcu_data_out : std_logic_vector(7 downto 0);
|
||||
signal mcu_data_in : std_logic_vector(7 downto 0);
|
||||
|
||||
signal lcd_data_in : std_logic_vector(15 downto 0);
|
||||
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
|
||||
signal lcd_data_out : std_logic_vector(15 downto 0);
|
||||
|
||||
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
signal lcd_reset_q : std_logic := '1';
|
||||
signal lcd_backlight_q : std_logic := '0';
|
||||
|
||||
signal sysoff_q : std_logic := '0';
|
||||
|
||||
signal audio_reset_q : std_logic := '1';
|
||||
|
||||
signal ref_en_q : std_logic := '0';
|
||||
|
||||
signal device_reset_q : std_logic := '1';
|
||||
|
||||
signal dir_read : boolean;
|
||||
signal dir_write : boolean;
|
||||
|
||||
signal lcd_read_strobe : boolean;
|
||||
signal lcd_write_strobe : boolean;
|
||||
signal lcd_write : boolean;
|
||||
|
||||
signal io_strobe : boolean;
|
||||
signal io_read_strobe : boolean;
|
||||
signal io_write_strobe : boolean;
|
||||
|
||||
signal reset_flag: boolean := false;
|
||||
signal reset_sync: std_logic := '1';
|
||||
signal counter: integer range 0 to 25000000 := 0; -- Adjust the count value for desired delay (e.g., 1 second with a 25 MHz clock)
|
||||
|
||||
constant COUNTER_MAX: integer := 25000000; -- Adjust this value to match the counter range
|
||||
|
||||
begin
|
||||
|
||||
-- I/O data
|
||||
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
|
||||
|
||||
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
|
||||
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
|
||||
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
|
||||
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
|
||||
|
||||
LCD_BACKLIGHT <= lcd_backlight_q;
|
||||
|
||||
SYSOFF <= sysoff_q;
|
||||
|
||||
MCU_LCD_TE <= LCD_TE;
|
||||
|
||||
|
||||
-- State management
|
||||
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
|
||||
dir_read <= (data_dir = to_mcu);
|
||||
dir_write <= (data_dir = from_mcu);
|
||||
|
||||
io_strobe <= (MCU_IO_STBX = '0');
|
||||
io_read_strobe <= io_strobe and dir_read;
|
||||
|
||||
lcd_read_strobe <= (MCU_LCD_RDX = '0');
|
||||
lcd_write <= not lcd_read_strobe;
|
||||
|
||||
-- LCD interface
|
||||
LCD_RS <= MCU_ADDR;
|
||||
LCD_RDX <= MCU_LCD_RDX;
|
||||
LCD_WRX <= MCU_LCD_WRX;
|
||||
|
||||
lcd_data_out <= lcd_data_out_q & mcu_data_in;
|
||||
lcd_data_in <= LCD_DB;
|
||||
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
|
||||
|
||||
-- Reference clock
|
||||
REF_EN <= ref_en_q;
|
||||
|
||||
-- Peripheral reset control
|
||||
LCD_RESETX <= not lcd_reset_q;
|
||||
AUDIO_RESETX <= not audio_reset_q;
|
||||
GPS_RESETX <= '1';
|
||||
|
||||
-- MCU interface
|
||||
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
|
||||
mcu_data_out_io <= switches;
|
||||
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
|
||||
|
||||
mcu_data_in <= MCU_D;
|
||||
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
|
||||
|
||||
-- Synchronous behaviors:
|
||||
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
|
||||
process(MCU_LCD_WRX, mcu_data_in)
|
||||
begin
|
||||
if falling_edge(MCU_LCD_WRX) then
|
||||
lcd_data_out_q <= mcu_data_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
|
||||
process(MCU_LCD_RDX, lcd_data_in)
|
||||
begin
|
||||
if rising_edge(MCU_LCD_RDX) then
|
||||
lcd_data_in_q <= lcd_data_in(7 downto 0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- I/O write (to resistive touch panel): Capture data from
|
||||
-- MCU and hold on TP pins until further notice.
|
||||
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
|
||||
begin
|
||||
if rising_edge(MCU_IO_STBX) and dir_write then
|
||||
if MCU_ADDR = '0' then
|
||||
tp_q <= mcu_data_in;
|
||||
else
|
||||
lcd_reset_q <= mcu_data_in(0);
|
||||
audio_reset_q <= mcu_data_in(1);
|
||||
ref_en_q <= mcu_data_in(6);
|
||||
lcd_backlight_q <= mcu_data_in(7);
|
||||
sysoff_q <= mcu_data_in(2);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end rtl;
|
||||
58
hardware/portapack_h4m/CPLD/README.md
Normal file
58
hardware/portapack_h4m/CPLD/README.md
Normal file
@ -0,0 +1,58 @@
|
||||
# Project Setup Guide
|
||||
|
||||
## Prerequisites
|
||||
|
||||
- Intel Quartus Prime
|
||||
- Supra-2023.02.b0-7773ca8a-win64-all
|
||||
|
||||
## Installation Steps
|
||||
|
||||
1. **Project Setup**
|
||||
|
||||
- Create a new AG256SL100 project in Quartus Prime
|
||||
- (Alternatively, copy an existing project)
|
||||
|
||||
2. **Code Implementation**
|
||||
|
||||
- Implement your code in the project
|
||||
- Compile the project to verify there are no errors
|
||||
- Ensure successful compilation before proceeding
|
||||
|
||||
3. **Supra Configuration**
|
||||
|
||||
- Launch Supra.exe
|
||||
- Navigate to: File → Project → Open Project
|
||||
- Select the H4M project when prompted
|
||||
- Select Tools → Migrate → Next
|
||||
|
||||
4. **Additional Setup**
|
||||
|
||||
- Follow the on-screen prompts
|
||||
- You will need to:
|
||||
- Open a second Quartus project
|
||||
- Execute a provided script
|
||||
|
||||
5. **Programming**
|
||||
|
||||
- In Supra, go to: Tools → Program
|
||||
- Click "Query device ID"
|
||||
- Verify the returned ID is: 0x00025610
|
||||
|
||||
6. **File Selection**
|
||||
|
||||
- Select the programming file (if not automatically loaded)
|
||||
- Use the .prg file from the Supra src folder (non-SRAM version)
|
||||
|
||||
7. **Programming Process**
|
||||
|
||||
- Click "Program" to begin
|
||||
- Note: The counter shows elapsed seconds, not progress percentage
|
||||
- Programming is complete when "USB driver disconnected" message appears
|
||||
|
||||
## Troubleshooting
|
||||
|
||||
If you encounter any issues, ensure:
|
||||
|
||||
- All prerequisites are properly installed
|
||||
- Project configurations are correct
|
||||
- Device connections are secure
|
||||
62
hardware/portapack_h4m/CPLD/Supra/H4M.proj
Normal file
62
hardware/portapack_h4m/CPLD/Supra/H4M.proj
Normal file
@ -0,0 +1,62 @@
|
||||
[GuiMigrateSetupPage]
|
||||
fromDir=../AG256SL100
|
||||
design=portapack_h4m_cpld
|
||||
device=AG256SL100
|
||||
veFile=
|
||||
ipFiles=
|
||||
backwardCompatible=false
|
||||
modeGroup=false
|
||||
modeQuartus=true
|
||||
modeSynplicity=false
|
||||
modeNative=false
|
||||
|
||||
[GuiMigrateRunPage]
|
||||
isMC=false
|
||||
count=
|
||||
jobs=
|
||||
seed=
|
||||
retry=0
|
||||
fitting=0
|
||||
fitter=0
|
||||
effort=0
|
||||
holdx=0
|
||||
skew=0
|
||||
skope=0
|
||||
preset=0
|
||||
adjust=0
|
||||
target=0
|
||||
tuning=0
|
||||
corner=0
|
||||
flow=0
|
||||
orgPlace=false
|
||||
quartusSdc=false
|
||||
probeForce=false
|
||||
probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0)
|
||||
probeCount=5
|
||||
probe0From=
|
||||
probe0Pad=
|
||||
probe1From=
|
||||
probe1Pad=
|
||||
probe2From=
|
||||
probe2Pad=
|
||||
probe3From=
|
||||
probe3Pad=
|
||||
probe4From=
|
||||
probe4Pad=
|
||||
|
||||
[GuiProgramScreen]
|
||||
hardwareId=0
|
||||
blasterSpeed=70
|
||||
prgFile=portapack_h4m_cpld.prg
|
||||
eraseBox=false
|
||||
cable=0
|
||||
runAction=program
|
||||
eraseChip=true
|
||||
eraseFrom=
|
||||
eraseTo=
|
||||
binFile=
|
||||
readFrom=
|
||||
readTo=
|
||||
|
||||
[MainWindow]
|
||||
recentFile.0=
|
||||
114
hardware/portapack_h4m/CPLD/Supra/af_batch.tcl
Normal file
114
hardware/portapack_h4m/CPLD/Supra/af_batch.tcl
Normal file
@ -0,0 +1,114 @@
|
||||
if {![info exist MODE ]} {set MODE QUARTUS}
|
||||
if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true}
|
||||
if {![info exists CORNER]} {set CORNER ""}
|
||||
if {![info exist COUNT]} {set COUNT 6}
|
||||
if {![info exist JOBS ]} {set JOBS 1}
|
||||
|
||||
if {![info exist SEEDS ]} {set SEEDS {0 0 0 0 666 888 }}
|
||||
if {![info exist EFFORTS ]} {set EFFORTS {highest highest highest highest high high }}
|
||||
if {![info exist FITTERS ]} {set FITTERS {hybrid hybrid hybrid hybrid hybrid hybrid }}
|
||||
if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }}
|
||||
if {![info exist SKEWS ]} {set SKEWS {advanced advanced advanced advanced aggressive basic }}
|
||||
if {![info exist HOLDXS ]} {set HOLDXS {default default default default default default}}
|
||||
|
||||
set bc_config "./bc_config.txt"
|
||||
if { [file exists $bc_config] } {
|
||||
alta::tcl_highlight "Using MC config $bc_config.\n"
|
||||
source "$bc_config"
|
||||
}
|
||||
|
||||
#######################################################################
|
||||
|
||||
proc get_rand_value { values } {
|
||||
if {[llength $values] == 0} { return {} }
|
||||
return [lindex $values [expr {int(rand()*10000)%[llength $values]}]]
|
||||
}
|
||||
|
||||
set results "bc_results"
|
||||
set summary "bc_summary.txt"
|
||||
file delete -force $results; file mkdir $results
|
||||
file delete $summary; print -nonewline "" >! $summary
|
||||
|
||||
set is_parallel [expr $JOBS > 1]
|
||||
set is_color ""; set is_gui ""; set is_quiet ""
|
||||
if { $is_parallel } {
|
||||
set is_gui "--quiet"
|
||||
} else {
|
||||
if { [alta::tcl_is_color] } { set is_color "--color" }
|
||||
if { [alta::tcl_is_gui ] } { set is_gui "--gui" }
|
||||
}
|
||||
|
||||
#######################################################################
|
||||
|
||||
set progs {}
|
||||
set titles {}
|
||||
for {set id 1} {$id <= $COUNT} {incr id} {
|
||||
set result_dir "$results/$id"
|
||||
file mkdir $result_dir
|
||||
|
||||
set seed [get_rand_value $SEEDS ]
|
||||
set effort [get_rand_value $EFFORTS ]
|
||||
set skew [get_rand_value $SKEWS ]
|
||||
set fitter [get_rand_value $FITTERS ]
|
||||
set fitting [get_rand_value $FITTINGS]
|
||||
set holdx [get_rand_value $HOLDXS ]
|
||||
|
||||
set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE]
|
||||
alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"]
|
||||
if { $CORNER != "" } {
|
||||
alta::lconcat prog [list -X "set CORNER $CORNER"]
|
||||
}
|
||||
alta::lconcat prog [list -X "set RESULT_DIR $result_dir"]
|
||||
if { $seed != "" } {
|
||||
alta::lconcat prog [list -X "set SEED $seed"]
|
||||
}
|
||||
if { $effort != "" } {
|
||||
alta::lconcat prog [list -X "set EFFORT $effort"]
|
||||
}
|
||||
if { $fitter != "" } {
|
||||
alta::lconcat prog [list -X "set FITTER $fitter"]
|
||||
}
|
||||
if { $fitting != "" } {
|
||||
alta::lconcat prog [list -X "set FITTING $fitting"]
|
||||
}
|
||||
if { $skew != "" } {
|
||||
alta::lconcat prog [list -X "set SKEW $skew"]
|
||||
}
|
||||
if { $holdx != "" } {
|
||||
alta::lconcat prog [list -X "set HOLDX $holdx"]
|
||||
}
|
||||
#alta::lconcat prog [list -F af_run.tcl]
|
||||
lappend progs $prog
|
||||
lappend titles "#$id $result_dir"
|
||||
}
|
||||
|
||||
#######################################################################
|
||||
|
||||
if { $is_parallel } {
|
||||
set bg_progs {}
|
||||
foreach bg_prog $progs {
|
||||
lappend bg_progs [lappend bg_prog $is_quiet]
|
||||
}
|
||||
bg_exec_queue $titles $bg_progs $JOBS
|
||||
}
|
||||
|
||||
#######################################################################
|
||||
|
||||
for {set id 1} {$id <= $COUNT} {incr id} {
|
||||
set result_dir "$results/$id"
|
||||
set prog [lindex $progs [expr $id-1]]
|
||||
set title [lindex $titles [expr $id-1]]
|
||||
if { ! $is_parallel } {
|
||||
puts $title
|
||||
puts $prog
|
||||
eval exec -ignorestderr $prog >&@ stdout
|
||||
}
|
||||
|
||||
print "***************************************************************************\n" >> $summary
|
||||
print "$title\n" >> $summary
|
||||
cat "$result_dir/alta_db/fmax.rpt" >> $summary
|
||||
cat "$result_dir/alta_db/xfer.rpt" >> $summary
|
||||
print "" >> $summary
|
||||
}
|
||||
|
||||
alta::tcl_highlight "Check $summary for result.\n"
|
||||
50
hardware/portapack_h4m/CPLD/Supra/af_ip.tcl
Normal file
50
hardware/portapack_h4m/CPLD/Supra/af_ip.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
set AGM_SUPRA true
|
||||
set DESIGN "portapack_h4m_cpld"
|
||||
set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp }
|
||||
lappend IPLIST alta_rv32
|
||||
|
||||
proc set_alta_partition {inst tag} {
|
||||
set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst]
|
||||
set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst]
|
||||
set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst]
|
||||
set section_id [string map { [ _ ] _ . _ | _} $inst_name]
|
||||
eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag"
|
||||
eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag"
|
||||
eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag"
|
||||
eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag"
|
||||
}
|
||||
|
||||
load_package flow
|
||||
if { $DESIGN == "" } {
|
||||
set DESIGN $::quartus(args)
|
||||
}
|
||||
project_open $DESIGN
|
||||
|
||||
set tag alta_auto
|
||||
if { [llength $IPLIST] > 0 } {
|
||||
# A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them.
|
||||
set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag]
|
||||
foreach_in_collection part $asgn_col {
|
||||
set section_id [lindex $part 0]
|
||||
eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id"
|
||||
}
|
||||
eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag"
|
||||
eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag"
|
||||
eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag"
|
||||
catch { execute_module -tool map }
|
||||
|
||||
foreach ip $IPLIST {
|
||||
foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] {
|
||||
set_alta_partition $inst $tag
|
||||
}
|
||||
foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] {
|
||||
set_alta_partition $inst $tag
|
||||
}
|
||||
}
|
||||
}
|
||||
eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation"
|
||||
|
||||
project_close
|
||||
|
||||
exit
|
||||
|
||||
79
hardware/portapack_h4m/CPLD/Supra/af_map.tcl
Normal file
79
hardware/portapack_h4m/CPLD/Supra/af_map.tcl
Normal file
@ -0,0 +1,79 @@
|
||||
map -import
|
||||
|
||||
if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
|
||||
set TOP_MODULE "$DESIGN"
|
||||
}
|
||||
if { ! [info exists DESIGN] } {
|
||||
set DESIGN "portapack_h4m_cpld"
|
||||
}
|
||||
if { ! [info exists TOP_MODULE] } {
|
||||
set TOP_MODULE "top"
|
||||
}
|
||||
|
||||
set verilogs { }
|
||||
if { [ llength $verilogs ] == 0 } {
|
||||
set verilogs "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/${DESIGN}.v"
|
||||
}
|
||||
foreach verilog $verilogs {
|
||||
read_verilog "$verilog"
|
||||
}
|
||||
|
||||
read_verilog -sv -lib +/agm/rodina/cells_sim.v
|
||||
read_verilog -sv -lib +/agm/common/m9k_bb.v
|
||||
read_verilog -sv -lib +/agm/common/altpll_bb.v
|
||||
hierarchy -check -top ${TOP_MODULE}
|
||||
|
||||
synth -run coarse -top ${DESIGN}
|
||||
|
||||
map proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
check
|
||||
opt
|
||||
|
||||
wreduce
|
||||
alumacc
|
||||
share
|
||||
opt
|
||||
fsm
|
||||
opt -fast
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
memory_bram -rules +/agm/common/brams.txt
|
||||
techmap -map +/agm/common/brams_map.v
|
||||
|
||||
opt -fast -mux_undef -undriven -fine -full
|
||||
memory_map
|
||||
opt -undriven -fine
|
||||
|
||||
techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v
|
||||
dffsr2dff
|
||||
dff2dffe -direct-match \$_DFF_*
|
||||
opt -full
|
||||
|
||||
techmap -map +/agm/rodina/cells_map.v
|
||||
agm_dffeas
|
||||
opt -full
|
||||
|
||||
clean -purge
|
||||
setundef -undriven -zero
|
||||
abc -markgroups -dff
|
||||
opt_expr -mux_undef -undriven -full
|
||||
opt_merge
|
||||
opt_rmdff
|
||||
opt_clean
|
||||
|
||||
abc -lut 4
|
||||
clean
|
||||
|
||||
techmap -map +/agm/rodina/cells_map.v
|
||||
dffinit -ff dffeas Q INIT
|
||||
clean -purge
|
||||
|
||||
hierarchy -check
|
||||
check -noinit
|
||||
|
||||
write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm
|
||||
# exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm
|
||||
|
||||
50
hardware/portapack_h4m/CPLD/Supra/af_quartus.tcl
Normal file
50
hardware/portapack_h4m/CPLD/Supra/af_quartus.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
set AGM_SUPRA true
|
||||
set RETRY 0
|
||||
set DESIGN "portapack_h4m_cpld"
|
||||
|
||||
if { [is_project_open] } {
|
||||
export_assignments
|
||||
}
|
||||
|
||||
set is_compatible false
|
||||
if { $is_compatible } {
|
||||
cd A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100
|
||||
qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog"
|
||||
} else {
|
||||
set FITTER_EFFORTS {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"}
|
||||
set SEEDS [list [expr int(rand()*100)] \
|
||||
[expr int(rand()*100)] \
|
||||
[expr int(rand()*100)] \
|
||||
[expr int(rand()*100)] \
|
||||
[expr int(rand()*100)]]
|
||||
set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \
|
||||
[expr rand()*5+0.1] \
|
||||
[expr rand()*5+0.1] \
|
||||
[expr rand()*5+0.1] \
|
||||
[expr rand()*5+0.1]]
|
||||
set ROUTER_EFFORTS [list [expr rand()*5+0.25] \
|
||||
[expr rand()*5+0.25] \
|
||||
[expr rand()*5+0.25] \
|
||||
[expr rand()*5+0.25] \
|
||||
[expr rand()*5+0.25]]
|
||||
|
||||
qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl"
|
||||
|
||||
load_package flow
|
||||
project_open $DESIGN
|
||||
|
||||
set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]]
|
||||
for {set nn -1} {$nn < $RETRY} {incr nn} {
|
||||
if {$nn >= 0} {
|
||||
set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\"
|
||||
set_global_assignment -name SEED [lindex $SEEDS $nn]
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn]
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER [lindex $ROUTER_EFFORTS $nn]
|
||||
}
|
||||
|
||||
set code [catch {execute_flow -compile} msg]
|
||||
if { $code == 0 } { break }
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
340
hardware/portapack_h4m/CPLD/Supra/af_run.tcl
Normal file
340
hardware/portapack_h4m/CPLD/Supra/af_run.tcl
Normal file
@ -0,0 +1,340 @@
|
||||
set ALTA_SUPRA true
|
||||
set sh_continue_on_error false
|
||||
set sh_echo_on_source true
|
||||
set sh_quiet_on_source true
|
||||
set cc_critical_as_fatal true
|
||||
set rt_incremental_route true
|
||||
set ta_report_auto 1
|
||||
set ta_report_auto_constraints $ta_report_auto
|
||||
|
||||
if { ! [info exists RESULT_DIR] } {
|
||||
set RESULT_DIR "."
|
||||
} elseif { ! [info exists alta_work] } {
|
||||
set alta_work "${RESULT_DIR}/alta_db"
|
||||
}
|
||||
if { ! [info exists DEVICE] } {
|
||||
set DEVICE "AG256SL100"
|
||||
}
|
||||
if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
|
||||
set TOP_MODULE "$DESIGN"
|
||||
}
|
||||
if { ! [info exists DESIGN] } {
|
||||
set DESIGN "portapack_h4m_cpld"
|
||||
}
|
||||
if { ! [info exists TOP_MODULE] } {
|
||||
set TOP_MODULE "top"
|
||||
}
|
||||
if { ! [info exists IP_FILES] } {
|
||||
set IP_FILES {}
|
||||
}
|
||||
if { ! [info exists VE_FILE] } {
|
||||
set VE_FILE ""
|
||||
}
|
||||
if { ! [info exists TIMING_DERATE] } {
|
||||
set TIMING_DERATE {1.000000 1.000000}
|
||||
}
|
||||
if { [info exists NO_ROUTE] && $NO_ROUTE } {
|
||||
set no_route "-no_route"
|
||||
} else {
|
||||
set no_route ""
|
||||
}
|
||||
if { ! [info exists RETRY] } { set RETRY 0 }
|
||||
if { ! [info exists SEED ] } { set SEED 666 }
|
||||
set seed_rand ""
|
||||
if { $SEED == 0 } { set seed_rand "-seed_rand" }
|
||||
if { [info exists QUARTUS_SDC] } {
|
||||
set sdc_remove_quartus_column_name $QUARTUS_SDC
|
||||
}
|
||||
if { ! [info exists ORG_PLACE] } { set ORG_PLACE false }
|
||||
if { ! [info exists MODE] } { set MODE "QUARTUS" }
|
||||
if { ! [info exists FLOW] } { set FLOW "ALL" }
|
||||
if { $FLOW == "PROBE" } {
|
||||
if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false }
|
||||
if { ! [info exists PREFIX] } { set PREFIX "probe_" }
|
||||
}
|
||||
if { ! [info exists PREFIX] } {
|
||||
set RESULT $DESIGN
|
||||
} else {
|
||||
set RESULT $PREFIX$DESIGN
|
||||
}
|
||||
if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" }
|
||||
set RUN "run"
|
||||
if { $FLOW == "CHECK" } {
|
||||
set RUN "check"
|
||||
} elseif { $FLOW == "PROBE" } {
|
||||
set RUN "probe"
|
||||
} elseif { $FLOW == "GEN" } {
|
||||
set RUN "gen"
|
||||
}
|
||||
|
||||
if { ! [info exists alta_logs] } {
|
||||
set alta_logs "${RESULT_DIR}/alta_logs"
|
||||
}
|
||||
file mkdir $alta_logs
|
||||
alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err"
|
||||
alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
|
||||
alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
|
||||
|
||||
set_seed_rand $SEED
|
||||
set ar_timing_derate ${TIMING_DERATE}
|
||||
|
||||
date_time
|
||||
if { [file exists "./${DESIGN}.pre.asf"] } {
|
||||
alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
|
||||
source "./${DESIGN}.pre.asf"
|
||||
}
|
||||
|
||||
set LOAD_DB false
|
||||
set LOAD_PLACE false
|
||||
set LOAD_ROUTE false
|
||||
if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
|
||||
set LOAD_DB true
|
||||
set LOAD_PLACE true
|
||||
set LOAD_ROUTE true
|
||||
} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
|
||||
set LOAD_DB true
|
||||
set LOAD_PLACE true
|
||||
}
|
||||
|
||||
set ORIGINAL_QSF "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/./portapack_h4m_cpld.qsf"
|
||||
set ORIGINAL_PIN "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.pin"
|
||||
|
||||
#################################################################################
|
||||
|
||||
while (1) {
|
||||
if { [info exists CORNER] } { set_mode -corner $CORNER; }
|
||||
|
||||
eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
|
||||
foreach ip_file $IP_FILES { read_ip $ip_file; }
|
||||
|
||||
|
||||
if { $FLOW == "GEN" } {
|
||||
if { ! [info exists CONFIG_BITS] } {
|
||||
set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin"
|
||||
}
|
||||
if { [llength $CONFIG_BITS] > 1 } {
|
||||
if { ! [info exists BOOT_BINARY] } {
|
||||
set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin"
|
||||
}
|
||||
if { ! [info exists CONFIG_ADDRESSES] } {
|
||||
set CONFIG_ADDRESSES ""
|
||||
}
|
||||
generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
|
||||
} else {
|
||||
set CONFIG_ROOT [file rootname [lindex $CONFIG_BITS 0]]
|
||||
set SLAVE_RBF "${CONFIG_ROOT}_slave.rbf"
|
||||
set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
|
||||
if { [file exists [lindex $CONFIG_BITS 0]] } {
|
||||
generate_binary -slave $SLAVE_RBF -inputs [lindex $CONFIG_BITS 0] -reverse
|
||||
generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
|
||||
}
|
||||
if { ! [info exists BOOT_BINARY] } {
|
||||
set BOOT_BINARY $MASTER_BINARY
|
||||
}
|
||||
}
|
||||
set PRG_FILE [file rootname $BOOT_BINARY].prg
|
||||
set AS_FILE [file rootname $BOOT_BINARY]_as.prg
|
||||
generate_programming_file $BOOT_BINARY -erase $ERASE \
|
||||
-program $PROGRAM -verify $VERIFY -offset $OFFSET \
|
||||
-prg $PRG_FILE -as $AS_FILE
|
||||
break
|
||||
}
|
||||
|
||||
if { $LOAD_DB } {
|
||||
load_db -top ${TOP_MODULE}
|
||||
set sdc "./${DESIGN}.adc"
|
||||
if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
|
||||
if { [file exists $sdc] } { read_sdc $sdc; }
|
||||
|
||||
} elseif { $MODE == "QUARTUS" } {
|
||||
set verilog ${DESIGN}.vo
|
||||
set is_migrated false
|
||||
if { ! [file exists $verilog] } {
|
||||
set verilog "./simulation/modelsim/${DESIGN}.vo"
|
||||
set is_migrated true
|
||||
}
|
||||
if { ! [file exists $verilog] } {
|
||||
error "Can not find design verilog file $verilog"
|
||||
}
|
||||
alta::tcl_highlight "Using design verilog file $verilog.\n"
|
||||
set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1]
|
||||
if { !$ret } { exit -1; }
|
||||
|
||||
set sdc "./${DESIGN}.adc"
|
||||
if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
|
||||
if { ! [file exists $sdc] } {
|
||||
alta::tcl_warn "Can not find design SDC file $sdc"
|
||||
} else {
|
||||
alta::tcl_highlight "Using design SDC file $sdc.\n"
|
||||
read_sdc $sdc
|
||||
}
|
||||
|
||||
} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
|
||||
set db_gclk_assignment_level 2
|
||||
set verilog ${DESIGN}.vqm
|
||||
set is_migrated false
|
||||
if { ! [file exists $verilog] } {
|
||||
error "Can not find design verilog file $verilog"
|
||||
}
|
||||
|
||||
set sdc "./${DESIGN}.adc"
|
||||
if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
|
||||
alta::tcl_highlight "Using design verilog file $verilog.\n"
|
||||
if { ! [file exists $sdc] } {
|
||||
alta::tcl_warn "Can not find design SDC file $sdc"
|
||||
set ret [read_design_and_pack -sdc $sdc -top ${TOP_MODULE} $verilog]
|
||||
} else {
|
||||
alta::tcl_highlight "Using design SDC file $sdc.\n"
|
||||
set ret [read_design_and_pack -top ${TOP_MODULE} $verilog]
|
||||
}
|
||||
if { !$ret } { exit -1; }
|
||||
|
||||
} else {
|
||||
error "Unsupported mode $MODE"
|
||||
}
|
||||
|
||||
if { $FLOW == "PACK" } { break }
|
||||
|
||||
if { [info exists FITTING] } {
|
||||
if { $FITTING == "Auto" } { set FITTING auto; }
|
||||
set_mode -fitting $FITTING
|
||||
}
|
||||
if { [info exists FITTER] } {
|
||||
if { $FITTER == "Auto" } {
|
||||
if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; }
|
||||
}
|
||||
if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; }
|
||||
set_mode -fitter $FITTER
|
||||
}
|
||||
if { [info exists EFFORT] } { set_mode -effort $EFFORT; }
|
||||
if { [info exists SKEW ] } { set_mode -skew $SKEW ; }
|
||||
if { [info exists SKOPE ] } { set_mode -skope $SKOPE ; }
|
||||
if { [info exists HOLDX ] } { set_mode -holdx $HOLDX; }
|
||||
if { [info exists TUNING] } { set_mode -tuning $TUNING; }
|
||||
if { [info exists TARGET] } { set_mode -target $TARGET; }
|
||||
if { [info exists PRESET] } { set_mode -preset $PRESET; }
|
||||
if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; }
|
||||
|
||||
set alta_aqf $::alta_work/alta.aqf
|
||||
if { $LOAD_DB } {
|
||||
# Empty
|
||||
} elseif { true } {
|
||||
if { [file exists $VE_FILE] } {
|
||||
set ORIGINAL_PIN ""
|
||||
} elseif { ! [file exists $ORIGINAL_PIN] } {
|
||||
if { $is_migrated } {
|
||||
error "Can not find design PIN file $ORIGINAL_PIN, please compile design first"
|
||||
}
|
||||
set ORIGINAL_PIN ""
|
||||
}
|
||||
if { [file exists $ORIGINAL_QSF] } {
|
||||
alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf
|
||||
} elseif { $is_migrated } {
|
||||
error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first"
|
||||
}
|
||||
}
|
||||
if { [file exists "$alta_aqf"] } {
|
||||
alta::tcl_highlight "Using AQF file $alta_aqf.\n"
|
||||
source "$alta_aqf"
|
||||
}
|
||||
if { [file exists "./${DESIGN}.asf"] } {
|
||||
alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n"
|
||||
source "./${DESIGN}.asf"
|
||||
}
|
||||
|
||||
if { $FLOW == "PROBE" } {
|
||||
set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
|
||||
if { !$ret } { exit -1 }
|
||||
|
||||
set force ""
|
||||
if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" }
|
||||
eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}"
|
||||
|
||||
} elseif { $FLOW == "CHECK" } {
|
||||
set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
|
||||
if { !$ret } { exit -1 }
|
||||
|
||||
if { [file exists "./${DESIGN}.chk"] } {
|
||||
alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n"
|
||||
source "./${DESIGN}.chk"
|
||||
place_design -dry
|
||||
check_design -rule led_guide
|
||||
} else {
|
||||
error "Can not find design CHECK file ${DESIGN}.chk"
|
||||
}
|
||||
|
||||
} else {
|
||||
set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io]
|
||||
if { !$ret } { exit -1 }
|
||||
|
||||
set org_place ""
|
||||
set load_place ""
|
||||
set load_route ""
|
||||
set quiet ""
|
||||
if { $ORG_PLACE } { set org_place "-org_place" ; }
|
||||
if { $LOAD_PLACE } { set load_place "-load_place"; }
|
||||
if { $LOAD_ROUTE } { set load_route "-load_route"; }
|
||||
eval "place_and_route_design $org_place $load_place $load_route \
|
||||
-retry $RETRY $seed_rand $quiet"
|
||||
}
|
||||
|
||||
date_time
|
||||
if { $FLOW != "CHECK" } {
|
||||
if { $FLOW != "PROBE" } {
|
||||
#report_timing -verbose 1 -file $::alta_work/timing.rpt.gz
|
||||
report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
|
||||
report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz
|
||||
report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
|
||||
report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz
|
||||
|
||||
set ta_report_auto_constraints 0
|
||||
report_timing -fmax -file $::alta_work/fmax.rpt
|
||||
report_timing -xfer -file $::alta_work/xfer.rpt
|
||||
set ta_report_auto_constraints $ta_report_auto
|
||||
|
||||
#set ta_coverage_limit "0.95 0.90"
|
||||
set ta_dump_uncovered 1
|
||||
report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
|
||||
#unset ta_coverage_limit
|
||||
unset ta_dump_uncovered
|
||||
|
||||
|
||||
if { ! [info exists rt_report_timing_fast] } {
|
||||
set rt_report_timing_fast false
|
||||
}
|
||||
if { $rt_report_timing_fast } {
|
||||
set_timing_corner fast
|
||||
route_delay -quiet
|
||||
report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz
|
||||
report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz
|
||||
report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz
|
||||
report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz
|
||||
set ta_report_auto_constraints 0
|
||||
report_timing -fmax -file $::alta_work/fmax_fast.rpt
|
||||
report_timing -xfer -file $::alta_work/xfer_fast.rpt
|
||||
set ta_report_auto_constraints $ta_report_auto
|
||||
}
|
||||
|
||||
write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
|
||||
}
|
||||
|
||||
bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
|
||||
bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
|
||||
bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
|
||||
generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
|
||||
-inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
|
||||
generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
|
||||
-inputs "${RESULT_DIR}/${RESULT}.bin"
|
||||
generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
|
||||
-as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
if { [file exists "./${DESIGN}.post.asf"] } {
|
||||
alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n"
|
||||
source "./${DESIGN}.post.asf"
|
||||
}
|
||||
date_time
|
||||
exit
|
||||
|
||||
266
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.aqf
Normal file
266
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.aqf
Normal file
@ -0,0 +1,266 @@
|
||||
set_global_assignment -name DEVICE_IO_STANDARD "3.3-V LVCMOS"
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET "OFF"
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_D
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_L
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_R
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_U
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_ROT_B
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_SEL
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_ROT_A
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[15]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[14]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[13]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[12]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[11]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[10]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[9]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[8]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[7]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[6]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[5]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[4]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[3]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[2]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[1]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[0]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RDX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RESETX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_TE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_WRX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_ADDR
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[7]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[6]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[5]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[4]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[3]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[2]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[1]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[0]
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_DIR
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_D
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_L
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_R
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_ROT_A
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_ROT_B
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_SEL
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_U
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_D
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_L
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_R
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_U
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to AUDIO_RESETX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_IO_STBX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_R
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_D
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_L
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_U
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_TE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_P2_8
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[15]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[14]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[13]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[12]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[11]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[10]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[9]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[8]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_ADDR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_DIR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_IO_STBX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to MCU_P2_8
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_TX_READY
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to GPS_TX_READY
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to REF_EN
|
||||
set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_RESETX
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to SYSOFF
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DEVICE_RESET
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DEVICE_RESET_V
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_RESETX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TX_READY
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RDX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RESETX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_TE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_WRX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to REF_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_D
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_L
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_ROT_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_ROT_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_SEL
|
||||
set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_U
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SYSOFF
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TIMEPULSE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TX_READY
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to REF_EN
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SYSOFF
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
|
||||
set_location_assignment PIN_57 -to AUDIO_RESETX
|
||||
set_location_assignment PIN_44 -to DEVICE_RESET
|
||||
set_location_assignment PIN_38 -to DEVICE_RESET_V
|
||||
set_location_assignment PIN_73 -to GPS_RESETX
|
||||
set_location_assignment PIN_74 -to GPS_TIMEPULSE
|
||||
set_location_assignment PIN_75 -to GPS_TX_READY
|
||||
set_location_assignment PIN_76 -to LCD_BACKLIGHT
|
||||
set_location_assignment PIN_99 -to LCD_DB[0]
|
||||
set_location_assignment PIN_87 -to LCD_DB[10]
|
||||
set_location_assignment PIN_86 -to LCD_DB[11]
|
||||
set_location_assignment PIN_85 -to LCD_DB[12]
|
||||
set_location_assignment PIN_84 -to LCD_DB[13]
|
||||
set_location_assignment PIN_83 -to LCD_DB[14]
|
||||
set_location_assignment PIN_82 -to LCD_DB[15]
|
||||
set_location_assignment PIN_98 -to LCD_DB[1]
|
||||
set_location_assignment PIN_97 -to LCD_DB[2]
|
||||
set_location_assignment PIN_96 -to LCD_DB[3]
|
||||
set_location_assignment PIN_95 -to LCD_DB[4]
|
||||
set_location_assignment PIN_92 -to LCD_DB[5]
|
||||
set_location_assignment PIN_91 -to LCD_DB[6]
|
||||
set_location_assignment PIN_90 -to LCD_DB[7]
|
||||
set_location_assignment PIN_89 -to LCD_DB[8]
|
||||
set_location_assignment PIN_88 -to LCD_DB[9]
|
||||
set_location_assignment PIN_1 -to LCD_RDX
|
||||
set_location_assignment PIN_100 -to LCD_RESETX
|
||||
set_location_assignment PIN_3 -to LCD_RS
|
||||
set_location_assignment PIN_4 -to LCD_TE
|
||||
set_location_assignment PIN_2 -to LCD_WRX
|
||||
set_location_assignment PIN_42 -to MCU_ADDR
|
||||
set_location_assignment PIN_72 -to MCU_DIR
|
||||
set_location_assignment PIN_35 -to MCU_D[0]
|
||||
set_location_assignment PIN_36 -to MCU_D[1]
|
||||
set_location_assignment PIN_33 -to MCU_D[2]
|
||||
set_location_assignment PIN_30 -to MCU_D[3]
|
||||
set_location_assignment PIN_28 -to MCU_D[4]
|
||||
set_location_assignment PIN_29 -to MCU_D[5]
|
||||
set_location_assignment PIN_27 -to MCU_D[6]
|
||||
set_location_assignment PIN_26 -to MCU_D[7]
|
||||
set_location_assignment PIN_41 -to MCU_IO_STBX
|
||||
set_location_assignment PIN_39 -to MCU_LCD_RDX
|
||||
set_location_assignment PIN_40 -to MCU_LCD_TE
|
||||
set_location_assignment PIN_71 -to MCU_LCD_WRX
|
||||
set_location_assignment PIN_43 -to MCU_P2_8
|
||||
set_location_assignment PIN_58 -to REF_EN
|
||||
set_location_assignment PIN_14 -to SW_D
|
||||
set_location_assignment PIN_37 -to SW_L
|
||||
set_location_assignment PIN_12 -to SW_R
|
||||
set_location_assignment PIN_15 -to SW_ROT_A
|
||||
set_location_assignment PIN_16 -to SW_ROT_B
|
||||
set_location_assignment PIN_17 -to SW_SEL
|
||||
set_location_assignment PIN_34 -to SW_U
|
||||
set_location_assignment PIN_47 -to SYSOFF
|
||||
set_location_assignment PIN_6 -to TP_D
|
||||
set_location_assignment PIN_7 -to TP_L
|
||||
set_location_assignment PIN_5 -to TP_R
|
||||
set_location_assignment PIN_8 -to TP_U
|
||||
38
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.asf
Normal file
38
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.asf
Normal file
@ -0,0 +1,38 @@
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_U~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_L~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_R~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_D~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[1]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[2]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[0]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[6]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[7]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[8]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[0]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[6]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[14]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[15]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[7]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[1]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[5]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[3]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[4]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[2]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[9]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[10]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[13]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[5]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[3]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[4]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[11]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[12]~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RDX~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_WRX~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RS~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_LCD_TE~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RESETX~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to REF_EN~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_BACKLIGHT~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to SYSOFF~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to AUDIO_RESETX~output false
|
||||
set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPS_RESETX~output false
|
||||
29
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.cellmap
Normal file
29
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.cellmap
Normal file
@ -0,0 +1,29 @@
|
||||
tp_q[3] clken_ctrl_X1_Y15_N0
|
||||
tp_q[4] clken_ctrl_X1_Y15_N0
|
||||
lcd_backlight_q clken_ctrl_X1_Y15_N1
|
||||
tp_q[0] clken_ctrl_X1_Y15_N0
|
||||
lcd_reset_q clken_ctrl_X1_Y15_N1
|
||||
tp_q[1] clken_ctrl_X1_Y15_N0
|
||||
audio_reset_q clken_ctrl_X1_Y15_N1
|
||||
tp_q[7] clken_ctrl_X1_Y15_N0
|
||||
tp_q[2] clken_ctrl_X1_Y15_N0
|
||||
tp_q[5] clken_ctrl_X1_Y15_N0
|
||||
ref_en_q clken_ctrl_X1_Y15_N1
|
||||
sysoff_q clken_ctrl_X1_Y15_N1
|
||||
tp_q[6] clken_ctrl_X1_Y15_N0
|
||||
lcd_data_in_q[0] clken_ctrl_X1_Y19_N0
|
||||
lcd_data_in_q[6] clken_ctrl_X1_Y19_N0
|
||||
lcd_data_out_q[1] clken_ctrl_X1_Y20_N0
|
||||
lcd_data_out_q[2] clken_ctrl_X1_Y20_N0
|
||||
lcd_data_out_q[6] clken_ctrl_X1_Y20_N0
|
||||
lcd_data_out_q[7] clken_ctrl_X1_Y20_N0
|
||||
lcd_data_out_q[0] clken_ctrl_X1_Y20_N0
|
||||
lcd_data_in_q[7] clken_ctrl_X1_Y21_N0
|
||||
lcd_data_in_q[1] clken_ctrl_X1_Y21_N0
|
||||
lcd_data_in_q[2] clken_ctrl_X1_Y24_N0
|
||||
lcd_data_in_q[4] clken_ctrl_X1_Y26_N0
|
||||
lcd_data_out_q[4] clken_ctrl_X1_Y26_N1
|
||||
lcd_data_out_q[3] clken_ctrl_X1_Y26_N1
|
||||
lcd_data_out_q[5] clken_ctrl_X1_Y26_N1
|
||||
lcd_data_in_q[3] clken_ctrl_X1_Y26_N0
|
||||
lcd_data_in_q[5] clken_ctrl_X1_Y26_N0
|
||||
859
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.pinmap
Normal file
859
hardware/portapack_h4m/CPLD/Supra/alta_db/alta.pinmap
Normal file
@ -0,0 +1,859 @@
|
||||
SW_L~input|datain SW_L~input|datain
|
||||
SW_L~input|oe SW_L~input|oe
|
||||
SW_L~input|outclk SW_L~input|outclk
|
||||
SW_L~input|outclkena SW_L~input|outclkena
|
||||
SW_L~input|inclk SW_L~input|inclk
|
||||
SW_L~input|inclkena SW_L~input|inclkena
|
||||
SW_L~input|areset SW_L~input|areset
|
||||
SW_L~input|sreset SW_L~input|sreset
|
||||
SW_L~input|combout SW_L~input|combout
|
||||
SW_L~input|padio SW_L~input|padio
|
||||
SW_R~input|datain SW_R~input|datain
|
||||
SW_R~input|oe SW_R~input|oe
|
||||
SW_R~input|outclk SW_R~input|outclk
|
||||
SW_R~input|outclkena SW_R~input|outclkena
|
||||
SW_R~input|inclk SW_R~input|inclk
|
||||
SW_R~input|inclkena SW_R~input|inclkena
|
||||
SW_R~input|areset SW_R~input|areset
|
||||
SW_R~input|sreset SW_R~input|sreset
|
||||
SW_R~input|combout SW_R~input|combout
|
||||
SW_R~input|padio SW_R~input|padio
|
||||
TP_U~output|datain TP_U~output|datain
|
||||
TP_U~output|oe TP_U~output|oe
|
||||
TP_U~output|outclk TP_U~output|outclk
|
||||
TP_U~output|outclkena TP_U~output|outclkena
|
||||
TP_U~output|inclk TP_U~output|inclk
|
||||
TP_U~output|inclkena TP_U~output|inclkena
|
||||
TP_U~output|areset TP_U~output|areset
|
||||
TP_U~output|sreset TP_U~output|sreset
|
||||
TP_U~output|padio TP_U~output|padio
|
||||
TP_L~output|datain TP_L~output|datain
|
||||
TP_L~output|oe TP_L~output|oe
|
||||
TP_L~output|outclk TP_L~output|outclk
|
||||
TP_L~output|outclkena TP_L~output|outclkena
|
||||
TP_L~output|inclk TP_L~output|inclk
|
||||
TP_L~output|inclkena TP_L~output|inclkena
|
||||
TP_L~output|areset TP_L~output|areset
|
||||
TP_L~output|sreset TP_L~output|sreset
|
||||
TP_L~output|padio TP_L~output|padio
|
||||
SW_ROT_B~input|datain SW_ROT_B~input|datain
|
||||
SW_ROT_B~input|oe SW_ROT_B~input|oe
|
||||
SW_ROT_B~input|outclk SW_ROT_B~input|outclk
|
||||
SW_ROT_B~input|outclkena SW_ROT_B~input|outclkena
|
||||
SW_ROT_B~input|inclk SW_ROT_B~input|inclk
|
||||
SW_ROT_B~input|inclkena SW_ROT_B~input|inclkena
|
||||
SW_ROT_B~input|areset SW_ROT_B~input|areset
|
||||
SW_ROT_B~input|sreset SW_ROT_B~input|sreset
|
||||
SW_ROT_B~input|combout SW_ROT_B~input|combout
|
||||
SW_ROT_B~input|padio SW_ROT_B~input|padio
|
||||
TP_R~output|datain TP_R~output|datain
|
||||
TP_R~output|oe TP_R~output|oe
|
||||
TP_R~output|outclk TP_R~output|outclk
|
||||
TP_R~output|outclkena TP_R~output|outclkena
|
||||
TP_R~output|inclk TP_R~output|inclk
|
||||
TP_R~output|inclkena TP_R~output|inclkena
|
||||
TP_R~output|areset TP_R~output|areset
|
||||
TP_R~output|sreset TP_R~output|sreset
|
||||
TP_R~output|padio TP_R~output|padio
|
||||
TP_D~output|datain TP_D~output|datain
|
||||
TP_D~output|oe TP_D~output|oe
|
||||
TP_D~output|outclk TP_D~output|outclk
|
||||
TP_D~output|outclkena TP_D~output|outclkena
|
||||
TP_D~output|inclk TP_D~output|inclk
|
||||
TP_D~output|inclkena TP_D~output|inclkena
|
||||
TP_D~output|areset TP_D~output|areset
|
||||
TP_D~output|sreset TP_D~output|sreset
|
||||
TP_D~output|padio TP_D~output|padio
|
||||
MCU_D[1]~output|datain MCU_D[1]~output|datain
|
||||
MCU_D[1]~output|oe MCU_D[1]~output|oe
|
||||
MCU_D[1]~output|outclk MCU_D[1]~output|outclk
|
||||
MCU_D[1]~output|outclkena MCU_D[1]~output|outclkena
|
||||
MCU_D[1]~output|inclk MCU_D[1]~output|inclk
|
||||
MCU_D[1]~output|inclkena MCU_D[1]~output|inclkena
|
||||
MCU_D[1]~output|areset MCU_D[1]~output|areset
|
||||
MCU_D[1]~output|sreset MCU_D[1]~output|sreset
|
||||
MCU_D[1]~output|combout MCU_D[1]~output|combout
|
||||
MCU_D[1]~output|padio MCU_D[1]~output|padio
|
||||
MCU_D[2]~output|datain MCU_D[2]~output|datain
|
||||
MCU_D[2]~output|oe MCU_D[2]~output|oe
|
||||
MCU_D[2]~output|outclk MCU_D[2]~output|outclk
|
||||
MCU_D[2]~output|outclkena MCU_D[2]~output|outclkena
|
||||
MCU_D[2]~output|inclk MCU_D[2]~output|inclk
|
||||
MCU_D[2]~output|inclkena MCU_D[2]~output|inclkena
|
||||
MCU_D[2]~output|areset MCU_D[2]~output|areset
|
||||
MCU_D[2]~output|sreset MCU_D[2]~output|sreset
|
||||
MCU_D[2]~output|combout MCU_D[2]~output|combout
|
||||
MCU_D[2]~output|padio MCU_D[2]~output|padio
|
||||
MCU_DIR~input|datain MCU_DIR~input|datain
|
||||
MCU_DIR~input|oe MCU_DIR~input|oe
|
||||
MCU_DIR~input|outclk MCU_DIR~input|outclk
|
||||
MCU_DIR~input|outclkena MCU_DIR~input|outclkena
|
||||
MCU_DIR~input|inclk MCU_DIR~input|inclk
|
||||
MCU_DIR~input|inclkena MCU_DIR~input|inclkena
|
||||
MCU_DIR~input|areset MCU_DIR~input|areset
|
||||
MCU_DIR~input|sreset MCU_DIR~input|sreset
|
||||
MCU_DIR~input|combout MCU_DIR~input|combout
|
||||
MCU_DIR~input|padio MCU_DIR~input|padio
|
||||
MCU_D[0]~output|datain MCU_D[0]~output|datain
|
||||
MCU_D[0]~output|oe MCU_D[0]~output|oe
|
||||
MCU_D[0]~output|outclk MCU_D[0]~output|outclk
|
||||
MCU_D[0]~output|outclkena MCU_D[0]~output|outclkena
|
||||
MCU_D[0]~output|inclk MCU_D[0]~output|inclk
|
||||
MCU_D[0]~output|inclkena MCU_D[0]~output|inclkena
|
||||
MCU_D[0]~output|areset MCU_D[0]~output|areset
|
||||
MCU_D[0]~output|sreset MCU_D[0]~output|sreset
|
||||
MCU_D[0]~output|combout MCU_D[0]~output|combout
|
||||
MCU_D[0]~output|padio MCU_D[0]~output|padio
|
||||
MCU_D[6]~output|datain MCU_D[6]~output|datain
|
||||
MCU_D[6]~output|oe MCU_D[6]~output|oe
|
||||
MCU_D[6]~output|outclk MCU_D[6]~output|outclk
|
||||
MCU_D[6]~output|outclkena MCU_D[6]~output|outclkena
|
||||
MCU_D[6]~output|inclk MCU_D[6]~output|inclk
|
||||
MCU_D[6]~output|inclkena MCU_D[6]~output|inclkena
|
||||
MCU_D[6]~output|areset MCU_D[6]~output|areset
|
||||
MCU_D[6]~output|sreset MCU_D[6]~output|sreset
|
||||
MCU_D[6]~output|combout MCU_D[6]~output|combout
|
||||
MCU_D[6]~output|padio MCU_D[6]~output|padio
|
||||
MCU_D[7]~output|datain MCU_D[7]~output|datain
|
||||
MCU_D[7]~output|oe MCU_D[7]~output|oe
|
||||
MCU_D[7]~output|outclk MCU_D[7]~output|outclk
|
||||
MCU_D[7]~output|outclkena MCU_D[7]~output|outclkena
|
||||
MCU_D[7]~output|inclk MCU_D[7]~output|inclk
|
||||
MCU_D[7]~output|inclkena MCU_D[7]~output|inclkena
|
||||
MCU_D[7]~output|areset MCU_D[7]~output|areset
|
||||
MCU_D[7]~output|sreset MCU_D[7]~output|sreset
|
||||
MCU_D[7]~output|combout MCU_D[7]~output|combout
|
||||
MCU_D[7]~output|padio MCU_D[7]~output|padio
|
||||
LCD_DB[8]~output|datain LCD_DB[8]~output|datain
|
||||
LCD_DB[8]~output|oe LCD_DB[8]~output|oe
|
||||
LCD_DB[8]~output|outclk LCD_DB[8]~output|outclk
|
||||
LCD_DB[8]~output|outclkena LCD_DB[8]~output|outclkena
|
||||
LCD_DB[8]~output|inclk LCD_DB[8]~output|inclk
|
||||
LCD_DB[8]~output|inclkena LCD_DB[8]~output|inclkena
|
||||
LCD_DB[8]~output|areset LCD_DB[8]~output|areset
|
||||
LCD_DB[8]~output|sreset LCD_DB[8]~output|sreset
|
||||
LCD_DB[8]~output|combout LCD_DB[8]~output|combout
|
||||
LCD_DB[8]~output|padio LCD_DB[8]~output|padio
|
||||
LCD_DB[0]~output|datain LCD_DB[0]~output|datain
|
||||
LCD_DB[0]~output|oe LCD_DB[0]~output|oe
|
||||
LCD_DB[0]~output|outclk LCD_DB[0]~output|outclk
|
||||
LCD_DB[0]~output|outclkena LCD_DB[0]~output|outclkena
|
||||
LCD_DB[0]~output|inclk LCD_DB[0]~output|inclk
|
||||
LCD_DB[0]~output|inclkena LCD_DB[0]~output|inclkena
|
||||
LCD_DB[0]~output|areset LCD_DB[0]~output|areset
|
||||
LCD_DB[0]~output|sreset LCD_DB[0]~output|sreset
|
||||
LCD_DB[0]~output|combout LCD_DB[0]~output|combout
|
||||
LCD_DB[0]~output|padio LCD_DB[0]~output|padio
|
||||
LCD_DB[6]~output|datain LCD_DB[6]~output|datain
|
||||
LCD_DB[6]~output|oe LCD_DB[6]~output|oe
|
||||
LCD_DB[6]~output|outclk LCD_DB[6]~output|outclk
|
||||
LCD_DB[6]~output|outclkena LCD_DB[6]~output|outclkena
|
||||
LCD_DB[6]~output|inclk LCD_DB[6]~output|inclk
|
||||
LCD_DB[6]~output|inclkena LCD_DB[6]~output|inclkena
|
||||
LCD_DB[6]~output|areset LCD_DB[6]~output|areset
|
||||
LCD_DB[6]~output|sreset LCD_DB[6]~output|sreset
|
||||
LCD_DB[6]~output|combout LCD_DB[6]~output|combout
|
||||
LCD_DB[6]~output|padio LCD_DB[6]~output|padio
|
||||
LCD_DB[14]~output|datain LCD_DB[14]~output|datain
|
||||
LCD_DB[14]~output|oe LCD_DB[14]~output|oe
|
||||
LCD_DB[14]~output|outclk LCD_DB[14]~output|outclk
|
||||
LCD_DB[14]~output|outclkena LCD_DB[14]~output|outclkena
|
||||
LCD_DB[14]~output|inclk LCD_DB[14]~output|inclk
|
||||
LCD_DB[14]~output|inclkena LCD_DB[14]~output|inclkena
|
||||
LCD_DB[14]~output|areset LCD_DB[14]~output|areset
|
||||
LCD_DB[14]~output|sreset LCD_DB[14]~output|sreset
|
||||
LCD_DB[14]~output|combout LCD_DB[14]~output|combout
|
||||
LCD_DB[14]~output|padio LCD_DB[14]~output|padio
|
||||
LCD_DB[15]~output|datain LCD_DB[15]~output|datain
|
||||
LCD_DB[15]~output|oe LCD_DB[15]~output|oe
|
||||
LCD_DB[15]~output|outclk LCD_DB[15]~output|outclk
|
||||
LCD_DB[15]~output|outclkena LCD_DB[15]~output|outclkena
|
||||
LCD_DB[15]~output|inclk LCD_DB[15]~output|inclk
|
||||
LCD_DB[15]~output|inclkena LCD_DB[15]~output|inclkena
|
||||
LCD_DB[15]~output|areset LCD_DB[15]~output|areset
|
||||
LCD_DB[15]~output|sreset LCD_DB[15]~output|sreset
|
||||
LCD_DB[15]~output|combout LCD_DB[15]~output|combout
|
||||
LCD_DB[15]~output|padio LCD_DB[15]~output|padio
|
||||
LCD_DB[7]~output|datain LCD_DB[7]~output|datain
|
||||
LCD_DB[7]~output|oe LCD_DB[7]~output|oe
|
||||
LCD_DB[7]~output|outclk LCD_DB[7]~output|outclk
|
||||
LCD_DB[7]~output|outclkena LCD_DB[7]~output|outclkena
|
||||
LCD_DB[7]~output|inclk LCD_DB[7]~output|inclk
|
||||
LCD_DB[7]~output|inclkena LCD_DB[7]~output|inclkena
|
||||
LCD_DB[7]~output|areset LCD_DB[7]~output|areset
|
||||
LCD_DB[7]~output|sreset LCD_DB[7]~output|sreset
|
||||
LCD_DB[7]~output|combout LCD_DB[7]~output|combout
|
||||
LCD_DB[7]~output|padio LCD_DB[7]~output|padio
|
||||
LCD_DB[1]~output|datain LCD_DB[1]~output|datain
|
||||
LCD_DB[1]~output|oe LCD_DB[1]~output|oe
|
||||
LCD_DB[1]~output|outclk LCD_DB[1]~output|outclk
|
||||
LCD_DB[1]~output|outclkena LCD_DB[1]~output|outclkena
|
||||
LCD_DB[1]~output|inclk LCD_DB[1]~output|inclk
|
||||
LCD_DB[1]~output|inclkena LCD_DB[1]~output|inclkena
|
||||
LCD_DB[1]~output|areset LCD_DB[1]~output|areset
|
||||
LCD_DB[1]~output|sreset LCD_DB[1]~output|sreset
|
||||
LCD_DB[1]~output|combout LCD_DB[1]~output|combout
|
||||
LCD_DB[1]~output|padio LCD_DB[1]~output|padio
|
||||
MCU_D[5]~output|datain MCU_D[5]~output|datain
|
||||
MCU_D[5]~output|oe MCU_D[5]~output|oe
|
||||
MCU_D[5]~output|outclk MCU_D[5]~output|outclk
|
||||
MCU_D[5]~output|outclkena MCU_D[5]~output|outclkena
|
||||
MCU_D[5]~output|inclk MCU_D[5]~output|inclk
|
||||
MCU_D[5]~output|inclkena MCU_D[5]~output|inclkena
|
||||
MCU_D[5]~output|areset MCU_D[5]~output|areset
|
||||
MCU_D[5]~output|sreset MCU_D[5]~output|sreset
|
||||
MCU_D[5]~output|combout MCU_D[5]~output|combout
|
||||
MCU_D[5]~output|padio MCU_D[5]~output|padio
|
||||
MCU_D[3]~output|datain MCU_D[3]~output|datain
|
||||
MCU_D[3]~output|oe MCU_D[3]~output|oe
|
||||
MCU_D[3]~output|outclk MCU_D[3]~output|outclk
|
||||
MCU_D[3]~output|outclkena MCU_D[3]~output|outclkena
|
||||
MCU_D[3]~output|inclk MCU_D[3]~output|inclk
|
||||
MCU_D[3]~output|inclkena MCU_D[3]~output|inclkena
|
||||
MCU_D[3]~output|areset MCU_D[3]~output|areset
|
||||
MCU_D[3]~output|sreset MCU_D[3]~output|sreset
|
||||
MCU_D[3]~output|combout MCU_D[3]~output|combout
|
||||
MCU_D[3]~output|padio MCU_D[3]~output|padio
|
||||
MCU_D[4]~output|datain MCU_D[4]~output|datain
|
||||
MCU_D[4]~output|oe MCU_D[4]~output|oe
|
||||
MCU_D[4]~output|outclk MCU_D[4]~output|outclk
|
||||
MCU_D[4]~output|outclkena MCU_D[4]~output|outclkena
|
||||
MCU_D[4]~output|inclk MCU_D[4]~output|inclk
|
||||
MCU_D[4]~output|inclkena MCU_D[4]~output|inclkena
|
||||
MCU_D[4]~output|areset MCU_D[4]~output|areset
|
||||
MCU_D[4]~output|sreset MCU_D[4]~output|sreset
|
||||
MCU_D[4]~output|combout MCU_D[4]~output|combout
|
||||
MCU_D[4]~output|padio MCU_D[4]~output|padio
|
||||
LCD_DB[2]~output|datain LCD_DB[2]~output|datain
|
||||
LCD_DB[2]~output|oe LCD_DB[2]~output|oe
|
||||
LCD_DB[2]~output|outclk LCD_DB[2]~output|outclk
|
||||
LCD_DB[2]~output|outclkena LCD_DB[2]~output|outclkena
|
||||
LCD_DB[2]~output|inclk LCD_DB[2]~output|inclk
|
||||
LCD_DB[2]~output|inclkena LCD_DB[2]~output|inclkena
|
||||
LCD_DB[2]~output|areset LCD_DB[2]~output|areset
|
||||
LCD_DB[2]~output|sreset LCD_DB[2]~output|sreset
|
||||
LCD_DB[2]~output|combout LCD_DB[2]~output|combout
|
||||
LCD_DB[2]~output|padio LCD_DB[2]~output|padio
|
||||
LCD_DB[9]~output|datain LCD_DB[9]~output|datain
|
||||
LCD_DB[9]~output|oe LCD_DB[9]~output|oe
|
||||
LCD_DB[9]~output|outclk LCD_DB[9]~output|outclk
|
||||
LCD_DB[9]~output|outclkena LCD_DB[9]~output|outclkena
|
||||
LCD_DB[9]~output|inclk LCD_DB[9]~output|inclk
|
||||
LCD_DB[9]~output|inclkena LCD_DB[9]~output|inclkena
|
||||
LCD_DB[9]~output|areset LCD_DB[9]~output|areset
|
||||
LCD_DB[9]~output|sreset LCD_DB[9]~output|sreset
|
||||
LCD_DB[9]~output|combout LCD_DB[9]~output|combout
|
||||
LCD_DB[9]~output|padio LCD_DB[9]~output|padio
|
||||
LCD_DB[10]~output|datain LCD_DB[10]~output|datain
|
||||
LCD_DB[10]~output|oe LCD_DB[10]~output|oe
|
||||
LCD_DB[10]~output|outclk LCD_DB[10]~output|outclk
|
||||
LCD_DB[10]~output|outclkena LCD_DB[10]~output|outclkena
|
||||
LCD_DB[10]~output|inclk LCD_DB[10]~output|inclk
|
||||
LCD_DB[10]~output|inclkena LCD_DB[10]~output|inclkena
|
||||
LCD_DB[10]~output|areset LCD_DB[10]~output|areset
|
||||
LCD_DB[10]~output|sreset LCD_DB[10]~output|sreset
|
||||
LCD_DB[10]~output|combout LCD_DB[10]~output|combout
|
||||
LCD_DB[10]~output|padio LCD_DB[10]~output|padio
|
||||
SW_D~input|datain SW_D~input|datain
|
||||
SW_D~input|oe SW_D~input|oe
|
||||
SW_D~input|outclk SW_D~input|outclk
|
||||
SW_D~input|outclkena SW_D~input|outclkena
|
||||
SW_D~input|inclk SW_D~input|inclk
|
||||
SW_D~input|inclkena SW_D~input|inclkena
|
||||
SW_D~input|areset SW_D~input|areset
|
||||
SW_D~input|sreset SW_D~input|sreset
|
||||
SW_D~input|combout SW_D~input|combout
|
||||
SW_D~input|padio SW_D~input|padio
|
||||
LCD_DB[13]~output|datain LCD_DB[13]~output|datain
|
||||
LCD_DB[13]~output|oe LCD_DB[13]~output|oe
|
||||
LCD_DB[13]~output|outclk LCD_DB[13]~output|outclk
|
||||
LCD_DB[13]~output|outclkena LCD_DB[13]~output|outclkena
|
||||
LCD_DB[13]~output|inclk LCD_DB[13]~output|inclk
|
||||
LCD_DB[13]~output|inclkena LCD_DB[13]~output|inclkena
|
||||
LCD_DB[13]~output|areset LCD_DB[13]~output|areset
|
||||
LCD_DB[13]~output|sreset LCD_DB[13]~output|sreset
|
||||
LCD_DB[13]~output|combout LCD_DB[13]~output|combout
|
||||
LCD_DB[13]~output|padio LCD_DB[13]~output|padio
|
||||
LCD_DB[5]~output|datain LCD_DB[5]~output|datain
|
||||
LCD_DB[5]~output|oe LCD_DB[5]~output|oe
|
||||
LCD_DB[5]~output|outclk LCD_DB[5]~output|outclk
|
||||
LCD_DB[5]~output|outclkena LCD_DB[5]~output|outclkena
|
||||
LCD_DB[5]~output|inclk LCD_DB[5]~output|inclk
|
||||
LCD_DB[5]~output|inclkena LCD_DB[5]~output|inclkena
|
||||
LCD_DB[5]~output|areset LCD_DB[5]~output|areset
|
||||
LCD_DB[5]~output|sreset LCD_DB[5]~output|sreset
|
||||
LCD_DB[5]~output|combout LCD_DB[5]~output|combout
|
||||
LCD_DB[5]~output|padio LCD_DB[5]~output|padio
|
||||
LCD_DB[3]~output|datain LCD_DB[3]~output|datain
|
||||
LCD_DB[3]~output|oe LCD_DB[3]~output|oe
|
||||
LCD_DB[3]~output|outclk LCD_DB[3]~output|outclk
|
||||
LCD_DB[3]~output|outclkena LCD_DB[3]~output|outclkena
|
||||
LCD_DB[3]~output|inclk LCD_DB[3]~output|inclk
|
||||
LCD_DB[3]~output|inclkena LCD_DB[3]~output|inclkena
|
||||
LCD_DB[3]~output|areset LCD_DB[3]~output|areset
|
||||
LCD_DB[3]~output|sreset LCD_DB[3]~output|sreset
|
||||
LCD_DB[3]~output|combout LCD_DB[3]~output|combout
|
||||
LCD_DB[3]~output|padio LCD_DB[3]~output|padio
|
||||
LCD_DB[4]~output|datain LCD_DB[4]~output|datain
|
||||
LCD_DB[4]~output|oe LCD_DB[4]~output|oe
|
||||
LCD_DB[4]~output|outclk LCD_DB[4]~output|outclk
|
||||
LCD_DB[4]~output|outclkena LCD_DB[4]~output|outclkena
|
||||
LCD_DB[4]~output|inclk LCD_DB[4]~output|inclk
|
||||
LCD_DB[4]~output|inclkena LCD_DB[4]~output|inclkena
|
||||
LCD_DB[4]~output|areset LCD_DB[4]~output|areset
|
||||
LCD_DB[4]~output|sreset LCD_DB[4]~output|sreset
|
||||
LCD_DB[4]~output|combout LCD_DB[4]~output|combout
|
||||
LCD_DB[4]~output|padio LCD_DB[4]~output|padio
|
||||
SW_ROT_A~input|datain SW_ROT_A~input|datain
|
||||
SW_ROT_A~input|oe SW_ROT_A~input|oe
|
||||
SW_ROT_A~input|outclk SW_ROT_A~input|outclk
|
||||
SW_ROT_A~input|outclkena SW_ROT_A~input|outclkena
|
||||
SW_ROT_A~input|inclk SW_ROT_A~input|inclk
|
||||
SW_ROT_A~input|inclkena SW_ROT_A~input|inclkena
|
||||
SW_ROT_A~input|areset SW_ROT_A~input|areset
|
||||
SW_ROT_A~input|sreset SW_ROT_A~input|sreset
|
||||
SW_ROT_A~input|combout SW_ROT_A~input|combout
|
||||
SW_ROT_A~input|padio SW_ROT_A~input|padio
|
||||
SW_U~input|datain SW_U~input|datain
|
||||
SW_U~input|oe SW_U~input|oe
|
||||
SW_U~input|outclk SW_U~input|outclk
|
||||
SW_U~input|outclkena SW_U~input|outclkena
|
||||
SW_U~input|inclk SW_U~input|inclk
|
||||
SW_U~input|inclkena SW_U~input|inclkena
|
||||
SW_U~input|areset SW_U~input|areset
|
||||
SW_U~input|sreset SW_U~input|sreset
|
||||
SW_U~input|combout SW_U~input|combout
|
||||
SW_U~input|padio SW_U~input|padio
|
||||
LCD_DB[11]~output|datain LCD_DB[11]~output|datain
|
||||
LCD_DB[11]~output|oe LCD_DB[11]~output|oe
|
||||
LCD_DB[11]~output|outclk LCD_DB[11]~output|outclk
|
||||
LCD_DB[11]~output|outclkena LCD_DB[11]~output|outclkena
|
||||
LCD_DB[11]~output|inclk LCD_DB[11]~output|inclk
|
||||
LCD_DB[11]~output|inclkena LCD_DB[11]~output|inclkena
|
||||
LCD_DB[11]~output|areset LCD_DB[11]~output|areset
|
||||
LCD_DB[11]~output|sreset LCD_DB[11]~output|sreset
|
||||
LCD_DB[11]~output|combout LCD_DB[11]~output|combout
|
||||
LCD_DB[11]~output|padio LCD_DB[11]~output|padio
|
||||
LCD_DB[12]~output|datain LCD_DB[12]~output|datain
|
||||
LCD_DB[12]~output|oe LCD_DB[12]~output|oe
|
||||
LCD_DB[12]~output|outclk LCD_DB[12]~output|outclk
|
||||
LCD_DB[12]~output|outclkena LCD_DB[12]~output|outclkena
|
||||
LCD_DB[12]~output|inclk LCD_DB[12]~output|inclk
|
||||
LCD_DB[12]~output|inclkena LCD_DB[12]~output|inclkena
|
||||
LCD_DB[12]~output|areset LCD_DB[12]~output|areset
|
||||
LCD_DB[12]~output|sreset LCD_DB[12]~output|sreset
|
||||
LCD_DB[12]~output|combout LCD_DB[12]~output|combout
|
||||
LCD_DB[12]~output|padio LCD_DB[12]~output|padio
|
||||
LCD_RDX~output|datain LCD_RDX~output|datain
|
||||
LCD_RDX~output|oe LCD_RDX~output|oe
|
||||
LCD_RDX~output|outclk LCD_RDX~output|outclk
|
||||
LCD_RDX~output|outclkena LCD_RDX~output|outclkena
|
||||
LCD_RDX~output|inclk LCD_RDX~output|inclk
|
||||
LCD_RDX~output|inclkena LCD_RDX~output|inclkena
|
||||
LCD_RDX~output|areset LCD_RDX~output|areset
|
||||
LCD_RDX~output|sreset LCD_RDX~output|sreset
|
||||
LCD_RDX~output|padio LCD_RDX~output|padio
|
||||
SW_SEL~input|datain SW_SEL~input|datain
|
||||
SW_SEL~input|oe SW_SEL~input|oe
|
||||
SW_SEL~input|outclk SW_SEL~input|outclk
|
||||
SW_SEL~input|outclkena SW_SEL~input|outclkena
|
||||
SW_SEL~input|inclk SW_SEL~input|inclk
|
||||
SW_SEL~input|inclkena SW_SEL~input|inclkena
|
||||
SW_SEL~input|areset SW_SEL~input|areset
|
||||
SW_SEL~input|sreset SW_SEL~input|sreset
|
||||
SW_SEL~input|combout SW_SEL~input|combout
|
||||
SW_SEL~input|padio SW_SEL~input|padio
|
||||
MCU_IO_STBX~input|datain MCU_IO_STBX~input|datain
|
||||
MCU_IO_STBX~input|oe MCU_IO_STBX~input|oe
|
||||
MCU_IO_STBX~input|outclk MCU_IO_STBX~input|outclk
|
||||
MCU_IO_STBX~input|outclkena MCU_IO_STBX~input|outclkena
|
||||
MCU_IO_STBX~input|inclk MCU_IO_STBX~input|inclk
|
||||
MCU_IO_STBX~input|inclkena MCU_IO_STBX~input|inclkena
|
||||
MCU_IO_STBX~input|areset MCU_IO_STBX~input|areset
|
||||
MCU_IO_STBX~input|sreset MCU_IO_STBX~input|sreset
|
||||
MCU_IO_STBX~input|combout MCU_IO_STBX~input|combout
|
||||
MCU_IO_STBX~input|padio MCU_IO_STBX~input|padio
|
||||
MCU_LCD_RDX~input|datain MCU_LCD_RDX~input|datain
|
||||
MCU_LCD_RDX~input|oe MCU_LCD_RDX~input|oe
|
||||
MCU_LCD_RDX~input|outclk MCU_LCD_RDX~input|outclk
|
||||
MCU_LCD_RDX~input|outclkena MCU_LCD_RDX~input|outclkena
|
||||
MCU_LCD_RDX~input|inclk MCU_LCD_RDX~input|inclk
|
||||
MCU_LCD_RDX~input|inclkena MCU_LCD_RDX~input|inclkena
|
||||
MCU_LCD_RDX~input|areset MCU_LCD_RDX~input|areset
|
||||
MCU_LCD_RDX~input|sreset MCU_LCD_RDX~input|sreset
|
||||
MCU_LCD_RDX~input|combout MCU_LCD_RDX~input|combout
|
||||
MCU_LCD_RDX~input|padio MCU_LCD_RDX~input|padio
|
||||
MCU_LCD_WRX~input|datain MCU_LCD_WRX~input|datain
|
||||
MCU_LCD_WRX~input|oe MCU_LCD_WRX~input|oe
|
||||
MCU_LCD_WRX~input|outclk MCU_LCD_WRX~input|outclk
|
||||
MCU_LCD_WRX~input|outclkena MCU_LCD_WRX~input|outclkena
|
||||
MCU_LCD_WRX~input|inclk MCU_LCD_WRX~input|inclk
|
||||
MCU_LCD_WRX~input|inclkena MCU_LCD_WRX~input|inclkena
|
||||
MCU_LCD_WRX~input|areset MCU_LCD_WRX~input|areset
|
||||
MCU_LCD_WRX~input|sreset MCU_LCD_WRX~input|sreset
|
||||
MCU_LCD_WRX~input|combout MCU_LCD_WRX~input|combout
|
||||
MCU_LCD_WRX~input|padio MCU_LCD_WRX~input|padio
|
||||
LCD_WRX~output|datain LCD_WRX~output|datain
|
||||
LCD_WRX~output|oe LCD_WRX~output|oe
|
||||
LCD_WRX~output|outclk LCD_WRX~output|outclk
|
||||
LCD_WRX~output|outclkena LCD_WRX~output|outclkena
|
||||
LCD_WRX~output|inclk LCD_WRX~output|inclk
|
||||
LCD_WRX~output|inclkena LCD_WRX~output|inclkena
|
||||
LCD_WRX~output|areset LCD_WRX~output|areset
|
||||
LCD_WRX~output|sreset LCD_WRX~output|sreset
|
||||
LCD_WRX~output|padio LCD_WRX~output|padio
|
||||
LCD_RS~output|datain LCD_RS~output|datain
|
||||
LCD_RS~output|oe LCD_RS~output|oe
|
||||
LCD_RS~output|outclk LCD_RS~output|outclk
|
||||
LCD_RS~output|outclkena LCD_RS~output|outclkena
|
||||
LCD_RS~output|inclk LCD_RS~output|inclk
|
||||
LCD_RS~output|inclkena LCD_RS~output|inclkena
|
||||
LCD_RS~output|areset LCD_RS~output|areset
|
||||
LCD_RS~output|sreset LCD_RS~output|sreset
|
||||
LCD_RS~output|padio LCD_RS~output|padio
|
||||
MCU_ADDR~input|datain MCU_ADDR~input|datain
|
||||
MCU_ADDR~input|oe MCU_ADDR~input|oe
|
||||
MCU_ADDR~input|outclk MCU_ADDR~input|outclk
|
||||
MCU_ADDR~input|outclkena MCU_ADDR~input|outclkena
|
||||
MCU_ADDR~input|inclk MCU_ADDR~input|inclk
|
||||
MCU_ADDR~input|inclkena MCU_ADDR~input|inclkena
|
||||
MCU_ADDR~input|areset MCU_ADDR~input|areset
|
||||
MCU_ADDR~input|sreset MCU_ADDR~input|sreset
|
||||
MCU_ADDR~input|combout MCU_ADDR~input|combout
|
||||
MCU_ADDR~input|padio MCU_ADDR~input|padio
|
||||
MCU_LCD_TE~output|datain MCU_LCD_TE~output|datain
|
||||
MCU_LCD_TE~output|oe MCU_LCD_TE~output|oe
|
||||
MCU_LCD_TE~output|outclk MCU_LCD_TE~output|outclk
|
||||
MCU_LCD_TE~output|outclkena MCU_LCD_TE~output|outclkena
|
||||
MCU_LCD_TE~output|inclk MCU_LCD_TE~output|inclk
|
||||
MCU_LCD_TE~output|inclkena MCU_LCD_TE~output|inclkena
|
||||
MCU_LCD_TE~output|areset MCU_LCD_TE~output|areset
|
||||
MCU_LCD_TE~output|sreset MCU_LCD_TE~output|sreset
|
||||
MCU_LCD_TE~output|padio MCU_LCD_TE~output|padio
|
||||
LCD_TE~input|datain LCD_TE~input|datain
|
||||
LCD_TE~input|oe LCD_TE~input|oe
|
||||
LCD_TE~input|outclk LCD_TE~input|outclk
|
||||
LCD_TE~input|outclkena LCD_TE~input|outclkena
|
||||
LCD_TE~input|inclk LCD_TE~input|inclk
|
||||
LCD_TE~input|inclkena LCD_TE~input|inclkena
|
||||
LCD_TE~input|areset LCD_TE~input|areset
|
||||
LCD_TE~input|sreset LCD_TE~input|sreset
|
||||
LCD_TE~input|combout LCD_TE~input|combout
|
||||
LCD_TE~input|padio LCD_TE~input|padio
|
||||
LCD_RESETX~output|datain LCD_RESETX~output|datain
|
||||
LCD_RESETX~output|oe LCD_RESETX~output|oe
|
||||
LCD_RESETX~output|outclk LCD_RESETX~output|outclk
|
||||
LCD_RESETX~output|outclkena LCD_RESETX~output|outclkena
|
||||
LCD_RESETX~output|inclk LCD_RESETX~output|inclk
|
||||
LCD_RESETX~output|inclkena LCD_RESETX~output|inclkena
|
||||
LCD_RESETX~output|areset LCD_RESETX~output|areset
|
||||
LCD_RESETX~output|sreset LCD_RESETX~output|sreset
|
||||
LCD_RESETX~output|padio LCD_RESETX~output|padio
|
||||
REF_EN~output|datain REF_EN~output|datain
|
||||
REF_EN~output|oe REF_EN~output|oe
|
||||
REF_EN~output|outclk REF_EN~output|outclk
|
||||
REF_EN~output|outclkena REF_EN~output|outclkena
|
||||
REF_EN~output|inclk REF_EN~output|inclk
|
||||
REF_EN~output|inclkena REF_EN~output|inclkena
|
||||
REF_EN~output|areset REF_EN~output|areset
|
||||
REF_EN~output|sreset REF_EN~output|sreset
|
||||
REF_EN~output|padio REF_EN~output|padio
|
||||
LCD_BACKLIGHT~output|datain LCD_BACKLIGHT~output|datain
|
||||
LCD_BACKLIGHT~output|oe LCD_BACKLIGHT~output|oe
|
||||
LCD_BACKLIGHT~output|outclk LCD_BACKLIGHT~output|outclk
|
||||
LCD_BACKLIGHT~output|outclkena LCD_BACKLIGHT~output|outclkena
|
||||
LCD_BACKLIGHT~output|inclk LCD_BACKLIGHT~output|inclk
|
||||
LCD_BACKLIGHT~output|inclkena LCD_BACKLIGHT~output|inclkena
|
||||
LCD_BACKLIGHT~output|areset LCD_BACKLIGHT~output|areset
|
||||
LCD_BACKLIGHT~output|sreset LCD_BACKLIGHT~output|sreset
|
||||
LCD_BACKLIGHT~output|padio LCD_BACKLIGHT~output|padio
|
||||
SYSOFF~output|datain SYSOFF~output|datain
|
||||
SYSOFF~output|oe SYSOFF~output|oe
|
||||
SYSOFF~output|outclk SYSOFF~output|outclk
|
||||
SYSOFF~output|outclkena SYSOFF~output|outclkena
|
||||
SYSOFF~output|inclk SYSOFF~output|inclk
|
||||
SYSOFF~output|inclkena SYSOFF~output|inclkena
|
||||
SYSOFF~output|areset SYSOFF~output|areset
|
||||
SYSOFF~output|sreset SYSOFF~output|sreset
|
||||
SYSOFF~output|padio SYSOFF~output|padio
|
||||
AUDIO_RESETX~output|datain AUDIO_RESETX~output|datain
|
||||
AUDIO_RESETX~output|oe AUDIO_RESETX~output|oe
|
||||
AUDIO_RESETX~output|outclk AUDIO_RESETX~output|outclk
|
||||
AUDIO_RESETX~output|outclkena AUDIO_RESETX~output|outclkena
|
||||
AUDIO_RESETX~output|inclk AUDIO_RESETX~output|inclk
|
||||
AUDIO_RESETX~output|inclkena AUDIO_RESETX~output|inclkena
|
||||
AUDIO_RESETX~output|areset AUDIO_RESETX~output|areset
|
||||
AUDIO_RESETX~output|sreset AUDIO_RESETX~output|sreset
|
||||
AUDIO_RESETX~output|padio AUDIO_RESETX~output|padio
|
||||
MCU_P2_8~input|datain MCU_P2_8~input|datain
|
||||
MCU_P2_8~input|oe MCU_P2_8~input|oe
|
||||
MCU_P2_8~input|outclk MCU_P2_8~input|outclk
|
||||
MCU_P2_8~input|outclkena MCU_P2_8~input|outclkena
|
||||
MCU_P2_8~input|inclk MCU_P2_8~input|inclk
|
||||
MCU_P2_8~input|inclkena MCU_P2_8~input|inclkena
|
||||
MCU_P2_8~input|areset MCU_P2_8~input|areset
|
||||
MCU_P2_8~input|sreset MCU_P2_8~input|sreset
|
||||
MCU_P2_8~input|combout MCU_P2_8~input|combout
|
||||
MCU_P2_8~input|padio MCU_P2_8~input|padio
|
||||
GPS_TX_READY~input|datain GPS_TX_READY~input|datain
|
||||
GPS_TX_READY~input|oe GPS_TX_READY~input|oe
|
||||
GPS_TX_READY~input|outclk GPS_TX_READY~input|outclk
|
||||
GPS_TX_READY~input|outclkena GPS_TX_READY~input|outclkena
|
||||
GPS_TX_READY~input|inclk GPS_TX_READY~input|inclk
|
||||
GPS_TX_READY~input|inclkena GPS_TX_READY~input|inclkena
|
||||
GPS_TX_READY~input|areset GPS_TX_READY~input|areset
|
||||
GPS_TX_READY~input|sreset GPS_TX_READY~input|sreset
|
||||
GPS_TX_READY~input|combout GPS_TX_READY~input|combout
|
||||
GPS_TX_READY~input|padio GPS_TX_READY~input|padio
|
||||
DEVICE_RESET~input|datain DEVICE_RESET~input|datain
|
||||
DEVICE_RESET~input|oe DEVICE_RESET~input|oe
|
||||
DEVICE_RESET~input|outclk DEVICE_RESET~input|outclk
|
||||
DEVICE_RESET~input|outclkena DEVICE_RESET~input|outclkena
|
||||
DEVICE_RESET~input|inclk DEVICE_RESET~input|inclk
|
||||
DEVICE_RESET~input|inclkena DEVICE_RESET~input|inclkena
|
||||
DEVICE_RESET~input|areset DEVICE_RESET~input|areset
|
||||
DEVICE_RESET~input|sreset DEVICE_RESET~input|sreset
|
||||
DEVICE_RESET~input|combout DEVICE_RESET~input|combout
|
||||
DEVICE_RESET~input|padio DEVICE_RESET~input|padio
|
||||
GPS_TIMEPULSE~input|datain GPS_TIMEPULSE~input|datain
|
||||
GPS_TIMEPULSE~input|oe GPS_TIMEPULSE~input|oe
|
||||
GPS_TIMEPULSE~input|outclk GPS_TIMEPULSE~input|outclk
|
||||
GPS_TIMEPULSE~input|outclkena GPS_TIMEPULSE~input|outclkena
|
||||
GPS_TIMEPULSE~input|inclk GPS_TIMEPULSE~input|inclk
|
||||
GPS_TIMEPULSE~input|inclkena GPS_TIMEPULSE~input|inclkena
|
||||
GPS_TIMEPULSE~input|areset GPS_TIMEPULSE~input|areset
|
||||
GPS_TIMEPULSE~input|sreset GPS_TIMEPULSE~input|sreset
|
||||
GPS_TIMEPULSE~input|combout GPS_TIMEPULSE~input|combout
|
||||
GPS_TIMEPULSE~input|padio GPS_TIMEPULSE~input|padio
|
||||
DEVICE_RESET_V~input|datain DEVICE_RESET_V~input|datain
|
||||
DEVICE_RESET_V~input|oe DEVICE_RESET_V~input|oe
|
||||
DEVICE_RESET_V~input|outclk DEVICE_RESET_V~input|outclk
|
||||
DEVICE_RESET_V~input|outclkena DEVICE_RESET_V~input|outclkena
|
||||
DEVICE_RESET_V~input|inclk DEVICE_RESET_V~input|inclk
|
||||
DEVICE_RESET_V~input|inclkena DEVICE_RESET_V~input|inclkena
|
||||
DEVICE_RESET_V~input|areset DEVICE_RESET_V~input|areset
|
||||
DEVICE_RESET_V~input|sreset DEVICE_RESET_V~input|sreset
|
||||
DEVICE_RESET_V~input|combout DEVICE_RESET_V~input|combout
|
||||
DEVICE_RESET_V~input|padio DEVICE_RESET_V~input|padio
|
||||
GPS_RESETX~output|datain GPS_RESETX~output|datain
|
||||
GPS_RESETX~output|oe GPS_RESETX~output|oe
|
||||
GPS_RESETX~output|outclk GPS_RESETX~output|outclk
|
||||
GPS_RESETX~output|outclkena GPS_RESETX~output|outclkena
|
||||
GPS_RESETX~output|inclk GPS_RESETX~output|inclk
|
||||
GPS_RESETX~output|inclkena GPS_RESETX~output|inclkena
|
||||
GPS_RESETX~output|areset GPS_RESETX~output|areset
|
||||
GPS_RESETX~output|sreset GPS_RESETX~output|sreset
|
||||
GPS_RESETX~output|padio GPS_RESETX~output|padio
|
||||
lcd_reset_q~0|dataa lcd_reset_q~0|A
|
||||
lcd_reset_q~0|datab lcd_reset_q~0|B
|
||||
lcd_reset_q~0|datac lcd_reset_q~0|C
|
||||
lcd_reset_q~0|datad lcd_reset_q~0|D
|
||||
lcd_reset_q~0|combout lcd_reset_q~0|LutOut
|
||||
|datac tp_q[3]|C
|
||||
tp_q[3]|clk tp_q[3]|Clk
|
||||
tp_q[3]|clrn tp_q[3]|AsyncReset
|
||||
tp_q[3]|sclr tp_q[3]|SyncReset
|
||||
tp_q[3]|sload tp_q[3]|SyncLoad
|
||||
tp_q[3]|q tp_q[3]|Q
|
||||
tp_q[4]~feeder|dataa tp_q[4]|A
|
||||
tp_q[4]~feeder|datab tp_q[4]|B
|
||||
tp_q[4]~feeder|datac tp_q[4]|C
|
||||
tp_q[4]~feeder|datad tp_q[4]|D
|
||||
tp_q[4]|clk tp_q[4]|Clk
|
||||
tp_q[4]|clrn tp_q[4]|AsyncReset
|
||||
tp_q[4]~feeder|combout tp_q[4]|LutOut
|
||||
tp_q[4]|q tp_q[4]|Q
|
||||
lcd_backlight_q~feeder|dataa lcd_backlight_q|A
|
||||
lcd_backlight_q~feeder|datab lcd_backlight_q|B
|
||||
lcd_backlight_q~feeder|datac lcd_backlight_q|C
|
||||
lcd_backlight_q~feeder|datad lcd_backlight_q|D
|
||||
lcd_backlight_q|clk lcd_backlight_q|Clk
|
||||
lcd_backlight_q|clrn lcd_backlight_q|AsyncReset
|
||||
lcd_backlight_q~feeder|combout lcd_backlight_q|LutOut
|
||||
lcd_backlight_q|q lcd_backlight_q|Q
|
||||
|datac tp_q[0]|C
|
||||
tp_q[0]|clk tp_q[0]|Clk
|
||||
tp_q[0]|clrn tp_q[0]|AsyncReset
|
||||
tp_q[0]|sclr tp_q[0]|SyncReset
|
||||
tp_q[0]|sload tp_q[0]|SyncLoad
|
||||
tp_q[0]|q tp_q[0]|Q
|
||||
lcd_reset_q~1|dataa lcd_reset_q|A
|
||||
lcd_reset_q~1|datab lcd_reset_q|B
|
||||
lcd_reset_q~1|datac lcd_reset_q|C
|
||||
lcd_reset_q~1|datad lcd_reset_q|D
|
||||
lcd_reset_q|clk lcd_reset_q|Clk
|
||||
lcd_reset_q|clrn lcd_reset_q|AsyncReset
|
||||
lcd_reset_q~1|combout lcd_reset_q|LutOut
|
||||
lcd_reset_q|q lcd_reset_q|Q
|
||||
|datac tp_q[1]|C
|
||||
tp_q[1]|clk tp_q[1]|Clk
|
||||
tp_q[1]|clrn tp_q[1]|AsyncReset
|
||||
tp_q[1]|sclr tp_q[1]|SyncReset
|
||||
tp_q[1]|sload tp_q[1]|SyncLoad
|
||||
tp_q[1]|q tp_q[1]|Q
|
||||
audio_reset_q~0|dataa audio_reset_q|A
|
||||
audio_reset_q~0|datab audio_reset_q|B
|
||||
audio_reset_q~0|datac audio_reset_q|C
|
||||
audio_reset_q~0|datad audio_reset_q|D
|
||||
audio_reset_q|clk audio_reset_q|Clk
|
||||
audio_reset_q|clrn audio_reset_q|AsyncReset
|
||||
audio_reset_q~0|combout audio_reset_q|LutOut
|
||||
audio_reset_q|q audio_reset_q|Q
|
||||
tp_q[7]~feeder|dataa tp_q[7]|A
|
||||
tp_q[7]~feeder|datab tp_q[7]|B
|
||||
tp_q[7]~feeder|datac tp_q[7]|C
|
||||
tp_q[7]~feeder|datad tp_q[7]|D
|
||||
tp_q[7]|clk tp_q[7]|Clk
|
||||
tp_q[7]|clrn tp_q[7]|AsyncReset
|
||||
tp_q[7]~feeder|combout tp_q[7]|LutOut
|
||||
tp_q[7]|q tp_q[7]|Q
|
||||
tp_q[2]~feeder|dataa tp_q[2]|A
|
||||
tp_q[2]~feeder|datab tp_q[2]|B
|
||||
tp_q[2]~feeder|datac tp_q[2]|C
|
||||
tp_q[2]~feeder|datad tp_q[2]|D
|
||||
tp_q[2]|clk tp_q[2]|Clk
|
||||
tp_q[2]|clrn tp_q[2]|AsyncReset
|
||||
tp_q[2]~feeder|combout tp_q[2]|LutOut
|
||||
tp_q[2]|q tp_q[2]|Q
|
||||
|datac tp_q[5]|C
|
||||
tp_q[5]|clk tp_q[5]|Clk
|
||||
tp_q[5]|clrn tp_q[5]|AsyncReset
|
||||
tp_q[5]|sclr tp_q[5]|SyncReset
|
||||
tp_q[5]|sload tp_q[5]|SyncLoad
|
||||
tp_q[5]|q tp_q[5]|Q
|
||||
ref_en_q~feeder|dataa ref_en_q|A
|
||||
ref_en_q~feeder|datab ref_en_q|B
|
||||
ref_en_q~feeder|datac ref_en_q|C
|
||||
ref_en_q~feeder|datad ref_en_q|D
|
||||
ref_en_q|clk ref_en_q|Clk
|
||||
ref_en_q|clrn ref_en_q|AsyncReset
|
||||
ref_en_q~feeder|combout ref_en_q|LutOut
|
||||
ref_en_q|q ref_en_q|Q
|
||||
tp_q[3]~0|dataa tp_q[3]~0|A
|
||||
tp_q[3]~0|datab tp_q[3]~0|B
|
||||
tp_q[3]~0|datac tp_q[3]~0|C
|
||||
tp_q[3]~0|datad tp_q[3]~0|D
|
||||
tp_q[3]~0|combout tp_q[3]~0|LutOut
|
||||
sysoff_q~feeder|dataa sysoff_q|A
|
||||
sysoff_q~feeder|datab sysoff_q|B
|
||||
sysoff_q~feeder|datac sysoff_q|C
|
||||
sysoff_q~feeder|datad sysoff_q|D
|
||||
sysoff_q|clk sysoff_q|Clk
|
||||
sysoff_q|clrn sysoff_q|AsyncReset
|
||||
sysoff_q~feeder|combout sysoff_q|LutOut
|
||||
sysoff_q|q sysoff_q|Q
|
||||
tp_q[6]~feeder|dataa tp_q[6]|A
|
||||
tp_q[6]~feeder|datab tp_q[6]|B
|
||||
tp_q[6]~feeder|datac tp_q[6]|C
|
||||
tp_q[6]~feeder|datad tp_q[6]|D
|
||||
tp_q[6]|clk tp_q[6]|Clk
|
||||
tp_q[6]|clrn tp_q[6]|AsyncReset
|
||||
tp_q[6]~feeder|combout tp_q[6]|LutOut
|
||||
tp_q[6]|q tp_q[6]|Q
|
||||
tp_q[3]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
tp_q[4]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
lcd_backlight_q|ena clken_ctrl_X1_Y15_N1|ClkEn
|
||||
tp_q[0]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
lcd_reset_q|ena clken_ctrl_X1_Y15_N1|ClkEn
|
||||
tp_q[1]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
audio_reset_q|ena clken_ctrl_X1_Y15_N1|ClkEn
|
||||
tp_q[7]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
tp_q[2]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
tp_q[5]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
ref_en_q|ena clken_ctrl_X1_Y15_N1|ClkEn
|
||||
sysoff_q|ena clken_ctrl_X1_Y15_N1|ClkEn
|
||||
tp_q[6]|ena clken_ctrl_X1_Y15_N0|ClkEn
|
||||
mcu_data_out[7]~15|dataa mcu_data_out[7]~15|A
|
||||
mcu_data_out[7]~15|datab mcu_data_out[7]~15|B
|
||||
mcu_data_out[7]~15|datac mcu_data_out[7]~15|C
|
||||
mcu_data_out[7]~15|datad mcu_data_out[7]~15|D
|
||||
mcu_data_out[7]~15|combout mcu_data_out[7]~15|LutOut
|
||||
mcu_data_out[6]~13|dataa mcu_data_out[6]~13|A
|
||||
mcu_data_out[6]~13|datab mcu_data_out[6]~13|B
|
||||
mcu_data_out[6]~13|datac mcu_data_out[6]~13|C
|
||||
mcu_data_out[6]~13|datad mcu_data_out[6]~13|D
|
||||
mcu_data_out[6]~13|combout mcu_data_out[6]~13|LutOut
|
||||
mcu_data_out[1]~3|dataa mcu_data_out[1]~3|A
|
||||
mcu_data_out[1]~3|datab mcu_data_out[1]~3|B
|
||||
mcu_data_out[1]~3|datac mcu_data_out[1]~3|C
|
||||
mcu_data_out[1]~3|datad mcu_data_out[1]~3|D
|
||||
mcu_data_out[1]~3|combout mcu_data_out[1]~3|LutOut
|
||||
mcu_data_out[0]~1|dataa mcu_data_out[0]~1|A
|
||||
mcu_data_out[0]~1|datab mcu_data_out[0]~1|B
|
||||
mcu_data_out[0]~1|datac mcu_data_out[0]~1|C
|
||||
mcu_data_out[0]~1|datad mcu_data_out[0]~1|D
|
||||
mcu_data_out[0]~1|combout mcu_data_out[0]~1|LutOut
|
||||
mcu_data_out[0]~0|dataa lcd_data_in_q[0]|A
|
||||
mcu_data_out[0]~0|datab lcd_data_in_q[0]|B
|
||||
mcu_data_out[0]~0|datac lcd_data_in_q[0]|C
|
||||
mcu_data_out[0]~0|datad lcd_data_in_q[0]|D
|
||||
lcd_data_in_q[0]|clk lcd_data_in_q[0]|Clk
|
||||
lcd_data_in_q[0]|clrn lcd_data_in_q[0]|AsyncReset
|
||||
lcd_data_in_q[0]|sclr lcd_data_in_q[0]|SyncReset
|
||||
lcd_data_in_q[0]|sload lcd_data_in_q[0]|SyncLoad
|
||||
mcu_data_out[0]~0|combout lcd_data_in_q[0]|LutOut
|
||||
lcd_data_in_q[0]|q lcd_data_in_q[0]|Q
|
||||
mcu_data_out[6]~12|dataa lcd_data_in_q[6]|A
|
||||
mcu_data_out[6]~12|datab lcd_data_in_q[6]|B
|
||||
mcu_data_out[6]~12|datac lcd_data_in_q[6]|C
|
||||
mcu_data_out[6]~12|datad lcd_data_in_q[6]|D
|
||||
lcd_data_in_q[6]|clk lcd_data_in_q[6]|Clk
|
||||
lcd_data_in_q[6]|clrn lcd_data_in_q[6]|AsyncReset
|
||||
lcd_data_in_q[6]|sclr lcd_data_in_q[6]|SyncReset
|
||||
lcd_data_in_q[6]|sload lcd_data_in_q[6]|SyncLoad
|
||||
mcu_data_out[6]~12|combout lcd_data_in_q[6]|LutOut
|
||||
lcd_data_in_q[6]|q lcd_data_in_q[6]|Q
|
||||
lcd_data_in_q[0]|ena clken_ctrl_X1_Y19_N0|ClkEn
|
||||
lcd_data_in_q[6]|ena clken_ctrl_X1_Y19_N0|ClkEn
|
||||
lcd_data_out_q[1]~feeder|dataa lcd_data_out_q[1]|A
|
||||
lcd_data_out_q[1]~feeder|datab lcd_data_out_q[1]|B
|
||||
lcd_data_out_q[1]~feeder|datac lcd_data_out_q[1]|C
|
||||
lcd_data_out_q[1]~feeder|datad lcd_data_out_q[1]|D
|
||||
lcd_data_out_q[1]|clk lcd_data_out_q[1]|Clk
|
||||
lcd_data_out_q[1]|clrn lcd_data_out_q[1]|AsyncReset
|
||||
lcd_data_out_q[1]~feeder|combout lcd_data_out_q[1]|LutOut
|
||||
lcd_data_out_q[1]|q lcd_data_out_q[1]|Q
|
||||
lcd_data_out_q[2]~feeder|dataa lcd_data_out_q[2]|A
|
||||
lcd_data_out_q[2]~feeder|datab lcd_data_out_q[2]|B
|
||||
lcd_data_out_q[2]~feeder|datac lcd_data_out_q[2]|C
|
||||
lcd_data_out_q[2]~feeder|datad lcd_data_out_q[2]|D
|
||||
lcd_data_out_q[2]|clk lcd_data_out_q[2]|Clk
|
||||
lcd_data_out_q[2]|clrn lcd_data_out_q[2]|AsyncReset
|
||||
lcd_data_out_q[2]~feeder|combout lcd_data_out_q[2]|LutOut
|
||||
lcd_data_out_q[2]|q lcd_data_out_q[2]|Q
|
||||
|datac lcd_data_out_q[6]|C
|
||||
lcd_data_out_q[6]|clk lcd_data_out_q[6]|Clk
|
||||
lcd_data_out_q[6]|clrn lcd_data_out_q[6]|AsyncReset
|
||||
lcd_data_out_q[6]|sclr lcd_data_out_q[6]|SyncReset
|
||||
lcd_data_out_q[6]|sload lcd_data_out_q[6]|SyncLoad
|
||||
lcd_data_out_q[6]|q lcd_data_out_q[6]|Q
|
||||
lcd_data_out_q[7]~feeder|dataa lcd_data_out_q[7]|A
|
||||
lcd_data_out_q[7]~feeder|datab lcd_data_out_q[7]|B
|
||||
lcd_data_out_q[7]~feeder|datac lcd_data_out_q[7]|C
|
||||
lcd_data_out_q[7]~feeder|datad lcd_data_out_q[7]|D
|
||||
lcd_data_out_q[7]|clk lcd_data_out_q[7]|Clk
|
||||
lcd_data_out_q[7]|clrn lcd_data_out_q[7]|AsyncReset
|
||||
lcd_data_out_q[7]~feeder|combout lcd_data_out_q[7]|LutOut
|
||||
lcd_data_out_q[7]|q lcd_data_out_q[7]|Q
|
||||
lcd_data_out_q[0]~feeder|dataa lcd_data_out_q[0]|A
|
||||
lcd_data_out_q[0]~feeder|datab lcd_data_out_q[0]|B
|
||||
lcd_data_out_q[0]~feeder|datac lcd_data_out_q[0]|C
|
||||
lcd_data_out_q[0]~feeder|datad lcd_data_out_q[0]|D
|
||||
lcd_data_out_q[0]|clk lcd_data_out_q[0]|Clk
|
||||
lcd_data_out_q[0]|clrn lcd_data_out_q[0]|AsyncReset
|
||||
lcd_data_out_q[0]~feeder|combout lcd_data_out_q[0]|LutOut
|
||||
lcd_data_out_q[0]|q lcd_data_out_q[0]|Q
|
||||
lcd_data_out_q[1]|ena clken_ctrl_X1_Y20_N0|ClkEn
|
||||
lcd_data_out_q[2]|ena clken_ctrl_X1_Y20_N0|ClkEn
|
||||
lcd_data_out_q[6]|ena clken_ctrl_X1_Y20_N0|ClkEn
|
||||
lcd_data_out_q[7]|ena clken_ctrl_X1_Y20_N0|ClkEn
|
||||
lcd_data_out_q[0]|ena clken_ctrl_X1_Y20_N0|ClkEn
|
||||
mcu_data_out[7]~14|dataa lcd_data_in_q[7]|A
|
||||
mcu_data_out[7]~14|datab lcd_data_in_q[7]|B
|
||||
mcu_data_out[7]~14|datac lcd_data_in_q[7]|C
|
||||
mcu_data_out[7]~14|datad lcd_data_in_q[7]|D
|
||||
lcd_data_in_q[7]|clk lcd_data_in_q[7]|Clk
|
||||
lcd_data_in_q[7]|clrn lcd_data_in_q[7]|AsyncReset
|
||||
lcd_data_in_q[7]|sclr lcd_data_in_q[7]|SyncReset
|
||||
lcd_data_in_q[7]|sload lcd_data_in_q[7]|SyncLoad
|
||||
mcu_data_out[7]~14|combout lcd_data_in_q[7]|LutOut
|
||||
lcd_data_in_q[7]|q lcd_data_in_q[7]|Q
|
||||
mcu_data_out[1]~2|dataa lcd_data_in_q[1]|A
|
||||
mcu_data_out[1]~2|datab lcd_data_in_q[1]|B
|
||||
mcu_data_out[1]~2|datac lcd_data_in_q[1]|C
|
||||
mcu_data_out[1]~2|datad lcd_data_in_q[1]|D
|
||||
lcd_data_in_q[1]|clk lcd_data_in_q[1]|Clk
|
||||
lcd_data_in_q[1]|clrn lcd_data_in_q[1]|AsyncReset
|
||||
lcd_data_in_q[1]|sclr lcd_data_in_q[1]|SyncReset
|
||||
lcd_data_in_q[1]|sload lcd_data_in_q[1]|SyncLoad
|
||||
mcu_data_out[1]~2|combout lcd_data_in_q[1]|LutOut
|
||||
lcd_data_in_q[1]|q lcd_data_in_q[1]|Q
|
||||
lcd_data_in_q[7]|ena clken_ctrl_X1_Y21_N0|ClkEn
|
||||
lcd_data_in_q[1]|ena clken_ctrl_X1_Y21_N0|ClkEn
|
||||
mcu_data_out[3]~7|dataa mcu_data_out[3]~7|A
|
||||
mcu_data_out[3]~7|datab mcu_data_out[3]~7|B
|
||||
mcu_data_out[3]~7|datac mcu_data_out[3]~7|C
|
||||
mcu_data_out[3]~7|datad mcu_data_out[3]~7|D
|
||||
mcu_data_out[3]~7|combout mcu_data_out[3]~7|LutOut
|
||||
mcu_data_out[4]~9|dataa mcu_data_out[4]~9|A
|
||||
mcu_data_out[4]~9|datab mcu_data_out[4]~9|B
|
||||
mcu_data_out[4]~9|datac mcu_data_out[4]~9|C
|
||||
mcu_data_out[4]~9|datad mcu_data_out[4]~9|D
|
||||
mcu_data_out[4]~9|combout mcu_data_out[4]~9|LutOut
|
||||
mcu_data_out[2]~5|dataa mcu_data_out[2]~5|A
|
||||
mcu_data_out[2]~5|datab mcu_data_out[2]~5|B
|
||||
mcu_data_out[2]~5|datac mcu_data_out[2]~5|C
|
||||
mcu_data_out[2]~5|datad mcu_data_out[2]~5|D
|
||||
mcu_data_out[2]~5|combout mcu_data_out[2]~5|LutOut
|
||||
mcu_data_out[5]~11|dataa mcu_data_out[5]~11|A
|
||||
mcu_data_out[5]~11|datab mcu_data_out[5]~11|B
|
||||
mcu_data_out[5]~11|datac mcu_data_out[5]~11|C
|
||||
mcu_data_out[5]~11|datad mcu_data_out[5]~11|D
|
||||
mcu_data_out[5]~11|combout mcu_data_out[5]~11|LutOut
|
||||
mcu_data_out[2]~4|dataa lcd_data_in_q[2]|A
|
||||
mcu_data_out[2]~4|datab lcd_data_in_q[2]|B
|
||||
mcu_data_out[2]~4|datac lcd_data_in_q[2]|C
|
||||
mcu_data_out[2]~4|datad lcd_data_in_q[2]|D
|
||||
lcd_data_in_q[2]|clk lcd_data_in_q[2]|Clk
|
||||
lcd_data_in_q[2]|clrn lcd_data_in_q[2]|AsyncReset
|
||||
lcd_data_in_q[2]|sclr lcd_data_in_q[2]|SyncReset
|
||||
lcd_data_in_q[2]|sload lcd_data_in_q[2]|SyncLoad
|
||||
mcu_data_out[2]~4|combout lcd_data_in_q[2]|LutOut
|
||||
lcd_data_in_q[2]|q lcd_data_in_q[2]|Q
|
||||
lcd_data_in_q[2]|ena clken_ctrl_X1_Y24_N0|ClkEn
|
||||
mcu_data_out[4]~8|dataa lcd_data_in_q[4]|A
|
||||
mcu_data_out[4]~8|datab lcd_data_in_q[4]|B
|
||||
mcu_data_out[4]~8|datac lcd_data_in_q[4]|C
|
||||
mcu_data_out[4]~8|datad lcd_data_in_q[4]|D
|
||||
lcd_data_in_q[4]|clk lcd_data_in_q[4]|Clk
|
||||
lcd_data_in_q[4]|clrn lcd_data_in_q[4]|AsyncReset
|
||||
lcd_data_in_q[4]|sclr lcd_data_in_q[4]|SyncReset
|
||||
lcd_data_in_q[4]|sload lcd_data_in_q[4]|SyncLoad
|
||||
mcu_data_out[4]~8|combout lcd_data_in_q[4]|LutOut
|
||||
lcd_data_in_q[4]|q lcd_data_in_q[4]|Q
|
||||
lcd_data_out_q[4]~feeder|dataa lcd_data_out_q[4]|A
|
||||
lcd_data_out_q[4]~feeder|datab lcd_data_out_q[4]|B
|
||||
lcd_data_out_q[4]~feeder|datac lcd_data_out_q[4]|C
|
||||
lcd_data_out_q[4]~feeder|datad lcd_data_out_q[4]|D
|
||||
lcd_data_out_q[4]|clk lcd_data_out_q[4]|Clk
|
||||
lcd_data_out_q[4]|clrn lcd_data_out_q[4]|AsyncReset
|
||||
lcd_data_out_q[4]~feeder|combout lcd_data_out_q[4]|LutOut
|
||||
lcd_data_out_q[4]|q lcd_data_out_q[4]|Q
|
||||
|datac lcd_data_out_q[3]|C
|
||||
lcd_data_out_q[3]|clk lcd_data_out_q[3]|Clk
|
||||
lcd_data_out_q[3]|clrn lcd_data_out_q[3]|AsyncReset
|
||||
lcd_data_out_q[3]|sclr lcd_data_out_q[3]|SyncReset
|
||||
lcd_data_out_q[3]|sload lcd_data_out_q[3]|SyncLoad
|
||||
lcd_data_out_q[3]|q lcd_data_out_q[3]|Q
|
||||
|datac lcd_data_out_q[5]|C
|
||||
lcd_data_out_q[5]|clk lcd_data_out_q[5]|Clk
|
||||
lcd_data_out_q[5]|clrn lcd_data_out_q[5]|AsyncReset
|
||||
lcd_data_out_q[5]|sclr lcd_data_out_q[5]|SyncReset
|
||||
lcd_data_out_q[5]|sload lcd_data_out_q[5]|SyncLoad
|
||||
lcd_data_out_q[5]|q lcd_data_out_q[5]|Q
|
||||
mcu_data_out[3]~6|dataa lcd_data_in_q[3]|A
|
||||
mcu_data_out[3]~6|datab lcd_data_in_q[3]|B
|
||||
mcu_data_out[3]~6|datac lcd_data_in_q[3]|C
|
||||
mcu_data_out[3]~6|datad lcd_data_in_q[3]|D
|
||||
lcd_data_in_q[3]|clk lcd_data_in_q[3]|Clk
|
||||
lcd_data_in_q[3]|clrn lcd_data_in_q[3]|AsyncReset
|
||||
lcd_data_in_q[3]|sclr lcd_data_in_q[3]|SyncReset
|
||||
lcd_data_in_q[3]|sload lcd_data_in_q[3]|SyncLoad
|
||||
mcu_data_out[3]~6|combout lcd_data_in_q[3]|LutOut
|
||||
lcd_data_in_q[3]|q lcd_data_in_q[3]|Q
|
||||
mcu_data_out[5]~10|dataa lcd_data_in_q[5]|A
|
||||
mcu_data_out[5]~10|datab lcd_data_in_q[5]|B
|
||||
mcu_data_out[5]~10|datac lcd_data_in_q[5]|C
|
||||
mcu_data_out[5]~10|datad lcd_data_in_q[5]|D
|
||||
lcd_data_in_q[5]|clk lcd_data_in_q[5]|Clk
|
||||
lcd_data_in_q[5]|clrn lcd_data_in_q[5]|AsyncReset
|
||||
lcd_data_in_q[5]|sclr lcd_data_in_q[5]|SyncReset
|
||||
lcd_data_in_q[5]|sload lcd_data_in_q[5]|SyncLoad
|
||||
mcu_data_out[5]~10|combout lcd_data_in_q[5]|LutOut
|
||||
lcd_data_in_q[5]|q lcd_data_in_q[5]|Q
|
||||
lcd_data_in_q[4]|ena clken_ctrl_X1_Y26_N0|ClkEn
|
||||
lcd_data_out_q[4]|ena clken_ctrl_X1_Y26_N1|ClkEn
|
||||
lcd_data_out_q[3]|ena clken_ctrl_X1_Y26_N1|ClkEn
|
||||
lcd_data_out_q[5]|ena clken_ctrl_X1_Y26_N1|ClkEn
|
||||
lcd_data_in_q[3]|ena clken_ctrl_X1_Y26_N0|ClkEn
|
||||
lcd_data_in_q[5]|ena clken_ctrl_X1_Y26_N0|ClkEn
|
||||
1935
hardware/portapack_h4m/CPLD/Supra/alta_db/alta_lib.v
Normal file
1935
hardware/portapack_h4m/CPLD/Supra/alta_db/alta_lib.v
Normal file
File diff suppressed because it is too large
Load Diff
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/coverage.rpt.gz
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/coverage.rpt.gz
Normal file
Binary file not shown.
2929
hardware/portapack_h4m/CPLD/Supra/alta_db/filtered.vx
Normal file
2929
hardware/portapack_h4m/CPLD/Supra/alta_db/filtered.vx
Normal file
File diff suppressed because it is too large
Load Diff
1975
hardware/portapack_h4m/CPLD/Supra/alta_db/flatten.vx
Normal file
1975
hardware/portapack_h4m/CPLD/Supra/alta_db/flatten.vx
Normal file
File diff suppressed because it is too large
Load Diff
0
hardware/portapack_h4m/CPLD/Supra/alta_db/fmax.rpt
Normal file
0
hardware/portapack_h4m/CPLD/Supra/alta_db/fmax.rpt
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/hold.rpt.gz
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/hold.rpt.gz
Normal file
Binary file not shown.
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/hold_summary.rpt.gz
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/hold_summary.rpt.gz
Normal file
Binary file not shown.
112
hardware/portapack_h4m/CPLD/Supra/alta_db/io.asf
Normal file
112
hardware/portapack_h4m/CPLD/Supra/alta_db/io.asf
Normal file
@ -0,0 +1,112 @@
|
||||
set_location_assignment -to MCU_D[7] PIN_26
|
||||
set_location_assignment -to MCU_D[6] PIN_27
|
||||
set_location_assignment -to MCU_D[5] PIN_29
|
||||
set_location_assignment -to MCU_D[4] PIN_28
|
||||
set_location_assignment -to MCU_D[3] PIN_30
|
||||
set_location_assignment -to MCU_D[2] PIN_33
|
||||
set_location_assignment -to MCU_D[1] PIN_36
|
||||
set_location_assignment -to MCU_D[0] PIN_35
|
||||
set_location_assignment -to MCU_DIR PIN_72
|
||||
set_location_assignment -to MCU_IO_STBX PIN_41
|
||||
set_location_assignment -to MCU_LCD_WRX PIN_71
|
||||
set_location_assignment -to MCU_ADDR PIN_42
|
||||
set_location_assignment -to MCU_LCD_TE PIN_40
|
||||
set_location_assignment -to MCU_P2_8 PIN_43
|
||||
set_location_assignment -to MCU_LCD_RDX PIN_39
|
||||
set_location_assignment -to TP_U PIN_8
|
||||
set_location_assignment -to TP_D PIN_6
|
||||
set_location_assignment -to TP_L PIN_7
|
||||
set_location_assignment -to TP_R PIN_5
|
||||
set_location_assignment -to SW_SEL PIN_17
|
||||
set_location_assignment -to SW_ROT_A PIN_15
|
||||
set_location_assignment -to SW_ROT_B PIN_16
|
||||
set_location_assignment -to SW_U PIN_34
|
||||
set_location_assignment -to SW_D PIN_14
|
||||
set_location_assignment -to SW_L PIN_37
|
||||
set_location_assignment -to SW_R PIN_12
|
||||
set_location_assignment -to LCD_RESETX PIN_100
|
||||
set_location_assignment -to LCD_RS PIN_3
|
||||
set_location_assignment -to LCD_WRX PIN_2
|
||||
set_location_assignment -to LCD_RDX PIN_1
|
||||
set_location_assignment -to LCD_DB[15] PIN_82
|
||||
set_location_assignment -to LCD_DB[14] PIN_83
|
||||
set_location_assignment -to LCD_DB[13] PIN_84
|
||||
set_location_assignment -to LCD_DB[12] PIN_85
|
||||
set_location_assignment -to LCD_DB[11] PIN_86
|
||||
set_location_assignment -to LCD_DB[10] PIN_87
|
||||
set_location_assignment -to LCD_DB[9] PIN_88
|
||||
set_location_assignment -to LCD_DB[8] PIN_89
|
||||
set_location_assignment -to LCD_DB[7] PIN_90
|
||||
set_location_assignment -to LCD_DB[6] PIN_91
|
||||
set_location_assignment -to LCD_DB[5] PIN_92
|
||||
set_location_assignment -to LCD_DB[4] PIN_95
|
||||
set_location_assignment -to LCD_DB[3] PIN_96
|
||||
set_location_assignment -to LCD_DB[2] PIN_97
|
||||
set_location_assignment -to LCD_DB[1] PIN_98
|
||||
set_location_assignment -to LCD_DB[0] PIN_99
|
||||
set_location_assignment -to LCD_TE PIN_4
|
||||
set_location_assignment -to LCD_BACKLIGHT PIN_76
|
||||
set_location_assignment -to SYSOFF PIN_47
|
||||
set_location_assignment -to AUDIO_RESETX PIN_57
|
||||
set_location_assignment -to REF_EN PIN_58
|
||||
set_location_assignment -to GPS_RESETX PIN_73
|
||||
set_location_assignment -to GPS_TX_READY PIN_75
|
||||
set_location_assignment -to GPS_TIMEPULSE PIN_74
|
||||
set_location_assignment -to DEVICE_RESET PIN_44
|
||||
set_location_assignment -to DEVICE_RESET_V PIN_38
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[7] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[6] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[5] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[4] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[3] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[2] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[1] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_D[0] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_DIR "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_IO_STBX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_LCD_WRX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_ADDR "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_LCD_TE "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_P2_8 "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to MCU_LCD_RDX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to TP_U "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to TP_D "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to TP_L "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to TP_R "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_SEL "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_ROT_A "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_ROT_B "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_U "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_D "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_L "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to SW_R "3.3V Schmitt Trigger Input"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_RESETX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_RS "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_WRX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_RDX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[15] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[14] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[13] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[12] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[11] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[10] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[9] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[8] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[7] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[6] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[5] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[4] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[3] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[2] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[1] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_DB[0] "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_TE "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to LCD_BACKLIGHT "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to SYSOFF "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to AUDIO_RESETX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to REF_EN "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to GPS_RESETX "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to GPS_TX_READY "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to GPS_TIMEPULSE "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to DEVICE_RESET "3.3-V LVCMOS"
|
||||
set_instance_assignment -name IO_STANDARD -to DEVICE_RESET_V "3.3-V LVCMOS"
|
||||
2565
hardware/portapack_h4m/CPLD/Supra/alta_db/packed.vx
Normal file
2565
hardware/portapack_h4m/CPLD/Supra/alta_db/packed.vx
Normal file
File diff suppressed because it is too large
Load Diff
125
hardware/portapack_h4m/CPLD/Supra/alta_db/place.tx
Normal file
125
hardware/portapack_h4m/CPLD/Supra/alta_db/place.tx
Normal file
@ -0,0 +1,125 @@
|
||||
ssWJbg*O-TSHdTjR
|
||||
^ykYUbZxhrN\/z*-xm-x%`T`=`t
|
||||
dvaLDM\AMw:PPKa/udH;9|0c0g0w
|
||||
n[tI{:2nE=y+CYTwlSOHfH<H<
|
||||
^G`"ZxhrN\/z*-xm-x%`T`Q`!
|
||||
d(J_A[~2aW[Ag\5RK4jN$%a%i%:
|
||||
;^':y?GyRP[qV/udH;9|0]0c0c
|
||||
6wnbVgw#6,-;rD&)jR)j ENEIEI
|
||||
o={ 0 `VZ'35qBwqBoW&WMW<
|
||||
G$<H2Hp.L5lFXMk1MkGu u u5
|
||||
q+9SoSuTRR`%*1i|1iqtHtHtR
|
||||
OA.-i-F,BmVCRlSwlSOH H Hm
|
||||
^ftYZYjSK|%$?p2Wp2^)M)M)|
|
||||
(`VmQm34^-|MvDd{Dd(8-8-8-
|
||||
%sf)i)B@SUoz*-xm-x%`U`t`!
|
||||
dP0vAvh,zw] cG cdKsK1Ks
|
||||
cAMn9nX-}J6~KpRKpc:}:O:f
|
||||
$f TATq0|n5LjN4jN$%C%i%i
|
||||
;|{+y+>#vBe29at9a;CkCvC]
|
||||
|>*qKqx4w /B;9H;9|0<0c0g
|
||||
6wnbnV{.MD&)jR)j ECEIEf
|
||||
o={ 0 `V>'35qBwqBoWXWMW&
|
||||
G$<H2Hp.NlFXMk1MkGu`u u`
|
||||
q+9SoSuTG`%*1i|1iqtJtHtH
|
||||
OA.-i*-XCRlSwlSOHBH HB
|
||||
^ftYZxhrN\/z*-xm-x%`=`t`!
|
||||
dP0vAt_] cG cdK+K!K+
|
||||
cAMn9a\5RK4jN$%,%|%{
|
||||
;|{+y"RGe29at9a;CwCvC_
|
||||
|.*hK[qqZ/udH;9|0w0g0<
|
||||
7w4bn,yDP5R)j EdECEf
|
||||
oP{+0 VZ'35qBwqBoWMWZW&
|
||||
G0<V2H.LlFXMk1MkGu u5u`
|
||||
qa9&oSTN`%*1i|1iqtHtltl
|
||||
On.!i-,yVCRlSwlSOHyH<H
|
||||
^]tkZYSM%$?p2Wp2^)|);)m
|
||||
(%VbQm47|MvDd{Dd(8"8C8"
|
||||
%8fGi)@5oz*-xm-x%`Q`!`S
|
||||
d20nAv,gw] cG cdK!K+K+
|
||||
cqM[9D@9gaX"6!`RKpc:v:&:}
|
||||
$7 cAG+A"Jq-5RK4jNQ/BQN`/$%,%C%{
|
||||
;8{ y|{+yR+Gefpt9a;C]C_C_
|
||||
|.*hK>*qKZqo/udH;98zv89+z|0=0n0g
|
||||
7w4b6wnbr[35qBwqBoWRWZW<
|
||||
G0<V2$<H2ynKFv71MkGu&u`uw
|
||||
qa9&o+9Sox3_%8\|1i!C?!icCqt^tNtR
|
||||
On.!i(mi:CYTwlSOH;H<H
|
||||
^xhZQNXz*-xm-x%`T`=`Q
|
||||
d_:Av]Q{G cdK+KsKz
|
||||
cgQ9A6!`RKpc:O:&:O
|
||||
$"lAM+JAs5RK4jN$%,%C%C
|
||||
;:"yR-?y>efpt9a;C_CkC!
|
||||
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|
||||
($b([=3\HwqBoWZW&WM
|
||||
GOy2VFv71MkGu u5uL
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
(cH0G_vwTQGdS_Q!^Qg<R(8"8<8^
|
||||
%{#pg|:3`p9^pCV9"S9TSvc:f:f:&
|
||||
$ oKQ`r=/9K89+zKo3KV3p|0<030g
|
||||
1X5*ko7yk2gkIJ2KL2}w5Gu u`u5
|
||||
q4$\!c-{g2Zq2&-Z1KZamK^)B)|);
|
||||
(cH0GSY{:cA|cjVAYzAWs1dK&KsK+
|
||||
cd0`^C| ray&ad4yGwy kg;C!CkC_
|
||||
|(k(BGGKA|0<0<0n
|
||||
jRbK{ M ECECEa
|
||||
oBw0xV<'oWXWXW<Z
|
||||
Gk12h.wlGu`u`u
|
||||
qi|o<TJ`qtJtJtRH
|
||||
OSwiJ,yVC<OHyHyHy
|
||||
^2WZ<SM%^)|)|)B
|
||||
(d{Q)47|(8"8"8R
|
||||
%xmi'@5o%`Q`Q`SU
|
||||
dcGAX,gwdK!K!Kzz
|
||||
8170
hardware/portapack_h4m/CPLD/Supra/alta_db/route.tx
Normal file
8170
hardware/portapack_h4m/CPLD/Supra/alta_db/route.tx
Normal file
File diff suppressed because it is too large
Load Diff
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/setup.rpt.gz
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/setup.rpt.gz
Normal file
Binary file not shown.
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/setup_summary.rpt.gz
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/alta_db/setup_summary.rpt.gz
Normal file
Binary file not shown.
0
hardware/portapack_h4m/CPLD/Supra/alta_db/xfer.rpt
Normal file
0
hardware/portapack_h4m/CPLD/Supra/alta_db/xfer.rpt
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.bin
Normal file
BIN
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.bin
Normal file
Binary file not shown.
5448
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.prg
Normal file
5448
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.prg
Normal file
File diff suppressed because it is too large
Load Diff
3
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qpf
Normal file
3
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qpf
Normal file
@ -0,0 +1,3 @@
|
||||
#QUARTUS_VERSION = "11.1"
|
||||
PROJECT_REVISION = "portapack_h4m_cpld"
|
||||
|
||||
115
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qsf
Normal file
115
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qsf
Normal file
@ -0,0 +1,115 @@
|
||||
# Design name Assignments, replace __design_name__ with actual design name
|
||||
# ========================
|
||||
set_global_assignment -name DEVICE EP4CE75F29C8
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY "top"
|
||||
set_global_assignment -name SEARCH_PATH "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\."
|
||||
|
||||
set_global_assignment -name VERILOG_FILE "A:\\Users\\jLynx\\Downloads\\Supra-2023.02.b0-7773ca8a-win64-all\\etc\\arch\\rodinia\\alta_sim.v"
|
||||
set_global_assignment -name VHDL_FILE "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\top.vhd"
|
||||
|
||||
set_global_assignment -name SDC_FILE "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\portapack_h4m_cpld.sdc"
|
||||
|
||||
set_global_assignment -name SDC_FILE .\\portapack_h4m_cpld_derate.sdc
|
||||
#set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE "atom_netlists/__design_name__.vqm"
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04 JANUARY 04, 2013"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
|
||||
#set_global_assignment -name SMART_RECOMPILE ON
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
#set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
|
||||
#set_global_assignment -name AUTO_ROM_RECOGNITION OFF
|
||||
#set_global_assignment -name AUTO_RAM_RECOGNITION OFF
|
||||
#set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF
|
||||
# set_instance_assignment -name PRESERVE_REGISTER ON -to *
|
||||
#set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER ON -to *
|
||||
#set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 0 -to *
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 4
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# start EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# ---------------------------------------
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
||||
|
||||
# end EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# -------------------------------------
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
|
||||
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION OFF
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING OFF
|
||||
|
||||
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
1
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.sdc
Normal file
1
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.sdc
Normal file
@ -0,0 +1 @@
|
||||
read_sdc -quiet "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc"
|
||||
@ -0,0 +1,806 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2023 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
|
||||
# Date created = 14:46:17 April 19, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus Prime software and is used
|
||||
# to preserve global assignments across Quartus Prime versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
|
||||
set_global_assignment -name IP_COMPONENT_INTERNAL Off
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
|
||||
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
|
||||
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZATION_MODE Balanced
|
||||
set_global_assignment -name ALLOW_REGISTER_MERGING On
|
||||
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name OCP_HW_EVAL -value OFF
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY -value "Cyclone V"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
|
||||
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name PRPOF_ID Off
|
||||
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
|
||||
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
|
||||
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
|
||||
set_global_assignment -name USE_CONF_DONE AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SCL AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SDA AUTO
|
||||
set_global_assignment -name USE_PWRMGT_ALERT AUTO
|
||||
set_global_assignment -name USE_INIT_DONE AUTO
|
||||
set_global_assignment -name USE_CVP_CONFDONE AUTO
|
||||
set_global_assignment -name USE_SEU_ERROR AUTO
|
||||
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
|
||||
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
|
||||
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN Off
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
|
||||
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name RESERVE_PR_PINS Off
|
||||
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
|
||||
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
|
||||
set_global_assignment -name SEU_FIT_REPORT Off
|
||||
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
|
||||
set_global_assignment -name POR_SCHEME "Instant ON"
|
||||
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name POF_VERIFY_PROTECT Off
|
||||
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
|
||||
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
|
||||
set_global_assignment -name GENERATE_PMSF_FILES On
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
@ -0,0 +1,2 @@
|
||||
set_timing_derate -late 2.0
|
||||
set_timing_derate -early 2.0
|
||||
5437
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_download.svf
Normal file
5437
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_download.svf
Normal file
File diff suppressed because it is too large
Load Diff
2342
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_routed.v
Normal file
2342
hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_routed.v
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue
Block a user