mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-12 16:37:36 +00:00
Initial firmware commit.
This commit is contained in:
Jared Boone
103
firmware/bootstrap/Makefile
Normal file
103
firmware/bootstrap/Makefile
Normal file
@@ -0,0 +1,103 @@
|
||||
#
|
||||
# Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
#
|
||||
# This file is part of PortaPack.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
|
||||
PATH_COMMON=../common
|
||||
PATH_APP_M0=../application
|
||||
TARGET_M0=$(PATH_APP_M0)/build/application
|
||||
APP_M0_SRC=$(PATH_APP_M0)/*.cpp $(PATH_APP_M0)/*.hpp $(PATH_COMMON)/*.cpp $(PATH_COMMON)/*.hpp
|
||||
|
||||
PATH_APP_M4=../baseband
|
||||
TARGET_M4=$(PATH_APP_M4)/build/baseband
|
||||
APP_M4_SRC=$(PATH_APP_M4)/*.cpp $(PATH_APP_M4)/*.hpp $(PATH_COMMON)/*.cpp $(PATH_COMMON)/*.hpp
|
||||
|
||||
TARGET=bootstrap
|
||||
|
||||
CC=arm-none-eabi-gcc
|
||||
LD=arm-none-eabi-gcc
|
||||
CP=arm-none-eabi-objcopy
|
||||
OBJDUMP=arm-none-eabi-objdump
|
||||
|
||||
CHIBIOS_PORTAPACK=../chibios-portapack
|
||||
CHIBIOS=../chibios
|
||||
INCLUDE=-I $(CHIBIOS)/os/ports/common/ARMCMx/CMSIS/include \
|
||||
-I $(CHIBIOS)/os/ports/common/ARMCMx \
|
||||
-I $(CHIBIOS_PORTAPACK)/os/hal/platforms/LPC43xx \
|
||||
-I $(CHIBIOS_PORTAPACK)/os/hal/platforms/LPC43xx_M4
|
||||
MCPU=cortex-m4
|
||||
CPUFLAGS=-mcpu=$(MCPU) -mthumb -mno-thumb-interwork -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING
|
||||
|
||||
COPT=-std=gnu99 \
|
||||
-Wall -Wextra -Wstrict-prototypes \
|
||||
$(CPUFLAGS) \
|
||||
-DLPC43XX -DLPC43XX_M4 \
|
||||
-Os \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-fno-builtin --specs=nano.specs
|
||||
|
||||
LDOPT=-nostartfiles \
|
||||
$(CPUFLAGS) \
|
||||
-D__START=main \
|
||||
-Wl,-Map=$(TARGET).map,--cref,--no-warn-mismatch,--library-path=.,--script=m4.ld,--gc-sections
|
||||
|
||||
all: image.bin
|
||||
|
||||
list: $(TARGET).lst $(TARGET_M4).lst $(TARGET_M0).lst
|
||||
|
||||
program: image.bin
|
||||
dfu-util --device 1fc9 --download ~/Desktop/binaries/hackrf-2014.08.1/firmware-bin/hackrf_one_usb_ram.dfu --reset
|
||||
sleep 1s
|
||||
hackrf_spiflash -w image.bin
|
||||
|
||||
image.bin: $(TARGET).elf $(TARGET_M4).elf $(TARGET_M0).elf
|
||||
$(CP) -O binary --pad-to 0x10000 $(TARGET).elf $(TARGET).bin
|
||||
$(CP) -O binary --pad-to 0x10000 $(TARGET_M4).elf m4.bin
|
||||
$(CP) -O binary $(TARGET_M0).elf m0.bin
|
||||
cat $(TARGET).bin m4.bin m0.bin >image.bin
|
||||
|
||||
$(TARGET).lst: $(TARGET).elf
|
||||
$(OBJDUMP) -S $(TARGET).elf >$(TARGET).lst
|
||||
|
||||
$(TARGET).elf: $(TARGET).o startup_ARMCM4.S
|
||||
$(LD) $(LDOPT) $(LIB) -o $(TARGET).elf $(TARGET).o startup_ARMCM4.S
|
||||
|
||||
$(TARGET).o: $(TARGET).c
|
||||
$(CC) $(COPT) $(INCLUDE) -c -o $(TARGET).o $(TARGET).c
|
||||
|
||||
$(TARGET_M4).lst: $(TARGET_M4).elf
|
||||
$(OBJDUMP) -S $(TARGET_M4).elf >$(TARGET_M4).lst
|
||||
|
||||
$(TARGET_M4).elf: $(PATH_APP_M4)/Makefile $(APP_M4_SRC)
|
||||
$(MAKE) -C $(PATH_APP_M4) -f Makefile
|
||||
|
||||
$(TARGET_M0).lst: $(TARGET_M0).elf
|
||||
$(OBJDUMP) -S $(TARGET_M0).elf >$(TARGET_M0).lst
|
||||
|
||||
$(TARGET_M0).elf: $(PATH_APP_M0)/Makefile $(APP_M0_SRC)
|
||||
$(MAKE) -C $(PATH_APP_M0) -f Makefile
|
||||
|
||||
clean:
|
||||
rm -f image.bin m0.bin m4.bin
|
||||
rm -f $(TARGET).o $(TARGET).elf $(TARGET).bin $(TARGET).lst $(TARGET).map
|
||||
$(MAKE) -C $(PATH_APP_M4) -f Makefile clean
|
||||
rm -f $(TARGET_M4).lst
|
||||
$(MAKE) -C $(PATH_APP_M0) -f Makefile clean
|
||||
rm -f $(TARGET_M0).lst
|
||||
113
firmware/bootstrap/bootstrap.c
Normal file
113
firmware/bootstrap/bootstrap.c
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of PortaPack.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <lpc43xx_m4.h>
|
||||
#include <nvic.h>
|
||||
|
||||
/* Bootstrap runs from SPIFI on the M4, immediately after the LPC43xx built-in
|
||||
* boot ROM runs.
|
||||
*/
|
||||
|
||||
/* After boot ROM executes:
|
||||
* PLL1 is at 288MHz (IRC * 24)
|
||||
* IDIVB_CTRL = PLL1 / 9 = 32MHz
|
||||
* IDIVC_CTRL = PLL1 / 3 = 96MHz
|
||||
* BASE_SPIFI_CLK.CLK_SEL = IDIVB
|
||||
*/
|
||||
|
||||
/* SPIFI config must run from RAM because SPIFI memory mode may/must be
|
||||
* re-initialized during the transition
|
||||
*/
|
||||
/* An ARM veneer will be created to make the long jump between code in the
|
||||
* SPIFI address range and the RAM address range.
|
||||
*/
|
||||
__attribute__ ((section("fast")))
|
||||
void configure_spifi(void) {
|
||||
/* Configure pins first, to enable SCK input buffer for feedback */
|
||||
|
||||
/* Configure SPIFI pins for maximum I/O rate */
|
||||
const uint32_t scu_spifi_io =
|
||||
(3 << 0) /* Function 3 */
|
||||
| (0 << 3) /* Disable pull-down */
|
||||
| (1 << 4) /* Disable pull-up */
|
||||
| (1 << 5) /* Fast slew rate */
|
||||
| (1 << 6) /* Enable input buffer */
|
||||
| (1 << 7) /* Disable input glitch filter */
|
||||
;
|
||||
LPC_SCU->SFSP3_3 = scu_spifi_io;
|
||||
LPC_SCU->SFSP3_4 = scu_spifi_io;
|
||||
LPC_SCU->SFSP3_5 = scu_spifi_io;
|
||||
LPC_SCU->SFSP3_6 = scu_spifi_io;
|
||||
LPC_SCU->SFSP3_7 = scu_spifi_io;
|
||||
LPC_SCU->SFSP3_8 = scu_spifi_io;
|
||||
|
||||
/* Tweak SPIFI mode */
|
||||
LPC_SPIFI->CTRL =
|
||||
(0xffff << 0) /* Timeout */
|
||||
| (0x1 << 16) /* CS high time in "clocks - 1" */
|
||||
| (0 << 21) /* 0: Attempt speculative prefetch on data accesses */
|
||||
| (0 << 22) /* 0: No interrupt on command ended */
|
||||
| (0 << 23) /* 0: SCK driven low after rising edge at which last bit of command is captured. Stays low while CS# is high. */
|
||||
| (0 << 27) /* 0: Cache prefetching enabled */
|
||||
| (0 << 28) /* 0: Quad protocol, IO3:0 */
|
||||
| (1 << 29) /* 1: Read data sampled on falling edge of clock */
|
||||
| (1 << 30) /* 1: Read data is sampled using feedback clock from SCK pin */
|
||||
| (0 << 31) /* 0: DMA request disabled */
|
||||
;
|
||||
|
||||
/* Throttle up the SPIFI interface to 96MHz (PLL1 / 3) */
|
||||
LPC_CGU->IDIVB_CTRL =
|
||||
(0 << 0) /* PD */
|
||||
| (1 << 2) /* IDIV (/2) */
|
||||
| (1 << 11) /* AUTOBLOCK */
|
||||
| (9 << 24) /* PLL1 */
|
||||
;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
#if 0
|
||||
/* Configure LEDs and make sure they're off to start */
|
||||
LPC_SCU->SFSP4_1 = (1 << 4) | 0; /* GPIO2[1] */
|
||||
LPC_SCU->SFSP4_2 = (1 << 4) | 0; /* GPIO2[2] */
|
||||
LPC_SCU->SFSP6_12 = (1 << 4) | 0; /* GPIO2[8] */
|
||||
LPC_GPIO->CLR[2] = (1 << 8) | (1 << 2) | (1 << 1);
|
||||
LPC_GPIO->DIR[2] = (1 << 8) | (1 << 2) | (1 << 1);
|
||||
|
||||
/* Indicate M4 is working */
|
||||
LPC_GPIO->SET[2] = (1 << 1);
|
||||
#endif
|
||||
configure_spifi();
|
||||
|
||||
/* NOTE: MEMMAP registers are ORed with the shadow address to create the
|
||||
* actual address.
|
||||
*/
|
||||
LPC_CREG->M0APPMEMMAP = LPC_SPIFI_DATA_CACHED_BASE + 0x20000;
|
||||
|
||||
/* Change M0APP_RST to 0 */
|
||||
LPC_RGU->RESET_CTRL[1] = 0;
|
||||
|
||||
while(1) {
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
void SystemInit(void) {
|
||||
}
|
||||
194
firmware/bootstrap/m4.ld
Normal file
194
firmware/bootstrap/m4.ld
Normal file
@@ -0,0 +1,194 @@
|
||||
/* Linker script to configure memory regions.
|
||||
* Need modifying for a specific board.
|
||||
* FLASH.ORIGIN: starting address of flash
|
||||
* FLASH.LENGTH: length of flash
|
||||
* RAM.ORIGIN: starting address of RAM bank 0
|
||||
* RAM.LENGTH: length of RAM bank 0
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx ) : ORIGIN = 0x00000000, LENGTH = 32k
|
||||
RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 96k
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
/* Text/code sections that need to be located in RAM */
|
||||
*(fast)
|
||||
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
257
firmware/bootstrap/startup_ARMCM4.S
Normal file
257
firmware/bootstrap/startup_ARMCM4.S
Normal file
@@ -0,0 +1,257 @@
|
||||
/* File: startup_ARMCM4.S
|
||||
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.0
|
||||
* Date: 16 August 2013
|
||||
*
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0xc00
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
.end
|
||||
Reference in New Issue
Block a user