mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-14 21:17:43 +00:00
Initial firmware commit.
This commit is contained in:
Jared Boone
141
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/hal_lld.c
Executable file
141
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/hal_lld.c
Executable file
@@ -0,0 +1,141 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Copyright (C) 2014 Jared Boone, ShareBrained Technology
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC43xx_M0/hal_lld.c
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* @brief LPC43xx M0 HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/* TODO: Somehow share this value between the M4 and M0 cores. The M0 always
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* runs at the same speed as the M4 core.
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*/
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static halclock_t hal_clock_f = LPC43XX_M0_CLK_PLL1_AT_BOOT;
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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halclock_t halLPCGetSystemClock(void) {
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return hal_clock_f;
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}
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void halLPCSetSystemClock(const halclock_t new_frequency) {
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hal_clock_f = new_frequency;
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}
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/* TODO: Expose RIT code, move elsewhere. */
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static void ritimer_stop(void) {
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LPC_RITIMER->CTRL =
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(0 << 0) /* RITINT */
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| (1 << 1) /* RITENCLR */
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| (1 << 2) /* RITENBR */
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| (0 << 3) /* RITEN */
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;
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}
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static void ritimer_start(void) {
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LPC_RITIMER->CTRL =
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(0 << 0) /* RITINT */
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| (1 << 1) /* RITENCLR */
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| (1 << 2) /* RITENBR */
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| (1 << 3) /* RITEN */
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;
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}
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void systick_adjust_period(const uint32_t counts_per_tick) {
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ritimer_stop();
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LPC_RITIMER->COMPVAL = counts_per_tick;
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LPC_RITIMER->COUNTER = 0;
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ritimer_start();
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}
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Initialize timer 3 to serve as a cycle (PCLK) counter. */
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LPC_TIMER3->TCR = (1 << 1); /* CRST=1 */
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LPC_TIMER3->TCR = 0; /* CRST=0 */
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LPC_TIMER3->TC = 0;
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LPC_TIMER3->PR = 0;
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LPC_TIMER3->TCR = (1 << 0); /* CEN=1 */
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/* Initialize repetitive interrupt timer (RIT) to act like SysTick for
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* operating system process timing.
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*/
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LPC_RITIMER->CTRL =
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(1 << 0) /* RITINT */
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| (1 << 1) /* RITENCLR */
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| (1 << 2) /* RITENBR */
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| (0 << 3) /* RITEN */
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;
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LPC_RITIMER->MASK = 0;
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systick_adjust_period(LPC43XX_M0_CLK_PLL1_AT_BOOT / CH_FREQUENCY - 1);
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nvicEnableVector(RITIMER_OR_WWDT_IRQn, CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
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}
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/* Work-around to use RITimer in place of SysTick, which isn't available on
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* the LPC43xx M0 core.
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*/
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CH_IRQ_HANDLER(RITimer_Or_WWDT_IRQHandler) {
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/* Same code as in SysTickVector */
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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LPC_RITIMER->CTRL =
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(1 << 0) /* RITINT */
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| (1 << 1) /* RITENCLR */
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| (1 << 2) /* RITENBR */
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| (1 << 3) /* RITEN */
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;
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CH_IRQ_EPILOGUE();
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}
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/** @} */
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157
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/hal_lld.h
Executable file
157
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/hal_lld.h
Executable file
@@ -0,0 +1,157 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Copyright (C) 2014 Jared Boone, ShareBrained Technology
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC43xx_M0/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "lpc43xx_m0.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "LPC43xx M0"
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Platform specific friendly IRQ names. */
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/*===========================================================================*/
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/**
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* @name IRQ VECTOR names
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* @{
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*/
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#define RTC_IRQHandler Vector40 /**< RTC */
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#define M4Core_IRQHandler Vector44 /**< Cortex-M4 */
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#define DMA_IRQHandler Vector48 /**< DMA */
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#define Ethernet_IRQHandler Vector54 /**< Ethernet */
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#define SDIO_IRQHandler Vector58 /**< SD/MMC */
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#define LCD_IRQHandler Vector5C /**< LCD */
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#define USB0_IRQHandler Vector60 /**< USB0: OTG */
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#define USB1_IRQHandler Vector64 /**< USB1 */
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#define SCT_IRQHandler Vector68 /**< SCT combined */
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#define RITimer_Or_WWDT_IRQHandler Vector6C /**< RI Timer or WWDT */
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#define Timer0_IRQHandler Vector70 /**< Timer 0 */
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#define GINT1_IRQHandler Vector74 /**< GPIO global interrupt 1 */
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#define PIN_INT4_IRQHandler Vector78 /**< GPIO pin interrupt 4 */
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#define Timer3_IRQHandler Vector7C /**< Timer 3 */
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#define MCPWM_IRQHandler Vector80 /**< Motor control PWM */
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#define ADC0_IRQHandler Vector84 /**< ADC0 */
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#define I2C0_Or_I2C1_IRQHandler Vector88 /**< I2C0 or I2C1 */
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#define SGPIO_IRQHandler Vector8C /**< SGPIO */
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#define SPI_Or_DAC_IRQHandler Vector90 /**< SPI or DAC */
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#define ADC1_IRQHandler Vector94 /**< ADC1 */
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#define SSP0_Or_SSP1_IRQHandler Vector98 /**< SSP0 or SSP1 */
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#define EventRouter_IRQHandler Vector9C /**< Event router */
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#define USART0_IRQHandler VectorA0 /**< USART0 */
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#define UART1_IRQHandler VectorA4 /**< UART1 */
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#define USART2_Or_C_CAN1_IRQHandler VectorA8 /**< USART2 or C_CAN1 */
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#define USART3_IRQHandler VectorAC /**< USART3 */
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#define I2S0_Or_I2S1_QEI_IRQHandler VectorB0 /**< I2S0 or I2S1 or QEI */
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#define C_CAN0_IRQHandler VectorB4 /**< C_CAN0 */
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#define SPIFI_Or_ADCHS_IRQHandler VectorB8 /**< SPIFI or ADCHS */
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#define M0SUB_IRQHandler VectorBC /**< M0SUB */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#define LPC43XX_M0_CLK_PLL1_AT_BOOT 96000000
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing a system clock frequency.
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*/
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typedef uint32_t halclock_t;
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/**
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* @brief Type of the realtime free counter value.
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*/
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typedef uint32_t halrtcnt_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the current value of the system free running counter.
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* @note This service is implemented by returning the content of timer 3's
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* TC (counter value) register.
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*
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* @return The value of the system free running counter of
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* type halrtcnt_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_value() (LPC_TIMER3->TC)
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/**
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* @brief Realtime counter frequency.
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* @note The DWT_CYCCNT register is incremented directly by the system
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* clock so this function returns STM32_HCLK.
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*
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* @return The realtime counter frequency of type halclock_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_frequency() halLPCGetSystemClock()
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void systick_adjust_period(const uint32_t counts_per_tick);
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halclock_t halLPCGetSystemClock(void);
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void halLPCSetSystemClock(const halclock_t new_frequency);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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@@ -0,0 +1,112 @@
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/*
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ChibiOS/RT - Copyright (C) 2014 Jared Boone, ShareBrained Technology
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
|
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distributed under the License is distributed on an "AS IS" BASIS,
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup lpc43xx_m0
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* @{
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*/
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#ifndef __LPC43XX_M0_H
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#define __LPC43XX_M0_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
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*/
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#define __CM0_REV 0 /*!< Core revision r0p0 */
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#define __MPU_PRESENT 0 /*!< LPC43XX M0 does not provide MPU */
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#define __NVIC_PRIO_BITS 2 /*!< LPC43XX M0 uses 2 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @brief LPC43XX M0 Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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typedef enum IRQn {
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/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
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Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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/****** LPC43xx M0 specific Interrupt Numbers *****************************************************************/
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RTC_IRQn = 0, /*!< 16 RTC */
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M4CORE_IRQn = 1, /*!< 17 Cortex-M4; Latched TXEV; for M0APP-M4 communication */
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DMA_IRQn = 2, /*!< 18 DMA */
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/* 3: 19 Reserved */
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/* 4: 20 ORed flash bank A, flash bank B, EEPROM interrupts */
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ETHERNET_IRQn = 5, /*!< 21 Ethernet */
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SDIO_IRQn = 6, /*!< 22 SD/MMC */
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LCD_IRQn = 7, /*!< 23 LCD */
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USB0_IRQn = 8, /*!< 24 OTG interrupt */
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USB1_IRQn = 9, /*!< 25 USB1 */
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SCT_IRQn = 10, /*!< 26 SCT combined interrupt */
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RITIMER_OR_WWDT_IRQn = 11, /*!< 27 RITIMER or WWDT */
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TIMER0_IRQn = 12, /*!< 28 TIMER0 */
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GINT1_IRQn = 13, /*!< 29 GPIO globak interrupt 1 */
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PIN_INT4_IRQn = 14, /*!< 30 GPIO pin interrupt 4 */
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TIMER3_IRQn = 15, /*!< 31 TIMER3 */
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MCPWM_IRQn = 16, /*!< 32 Motor control PWM */
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ADC0_IRQn = 17, /*!< 33 ADC0 */
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I2C0_OR_I2C1_IRQn = 18, /*!< 34 I2C0 or I2C1 */
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SGPIO_IRQn = 19, /*!< 35 SGPIO */
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SPI_OR_DAC_IRQn = 20, /*!< 36 SPI interrupt ORed with DAC interrupt */
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ADC1_IRQn = 21, /*!< 37 ADC1 */
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SSP0_OR_SSP1_IRQn = 22, /*!< 38 SSP0 interrupt ORed with SSP1 interrupt */
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EVENTROUTER_IRQn = 23, /*!< 39 Event router */
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USART0_IRQn = 24, /*!< 40 USART0 */
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UART1_IRQn = 25, /*!< 41 Combined UART interrupt with Modem interrupt */
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USART2_OR_C_CAN1_IRQn = 26, /*!< 42 USART2 interrupt ORed with C_CAN1 interrupt */
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USART3_IRQn = 27, /*!< 43 Combined USART interrupt with IrDA interrupt */
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I2S0_OR_I2S1_QEI_IRQn = 28, /*!< 44 I2S0 OR I2S1 OR QEI interrupt */
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C_CAN0_IRQn = 29, /*!< 45 C_CAN0 */
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SPIFI_OR_ADCHS_IRQn = 30, /*!< 46 SPIFI OR ADCHS interrupt */
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M0SUB_IRQn = 31, /*!< 47 M0SUB core */
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} IRQn_Type;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#include "lpc43xx.inc"
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#endif /* __LPC43XX_M0_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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13
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/platform.mk
Executable file
13
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M0/platform.mk
Executable file
@@ -0,0 +1,13 @@
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# List of all the LPC43xx M0 platform files.
|
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PLATFORMSRC = ${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx_M0/hal_lld.c \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/gpt_lld.c \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/i2c_lld.c \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/pal_lld.c \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/rtc_lld.c \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/sdc_lld.c \
|
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/serial_lld.c \
|
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/spi_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx_M0 \
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${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx
|
||||
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