mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-15 01:57:50 +00:00
Initial firmware commit.
This commit is contained in:
Jared Boone
91
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c
Executable file
91
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c
Executable file
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
Copyright (C) 2014 Jared Boone, ShareBrained Technology
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file LPC43xx_M4/hal_lld.c
|
||||
* @brief LPC43xx M4 HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
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||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* TODO: Somehow share this value between the M4 and M0 cores. The M0 always
|
||||
* runs at the same speed as the M4 core.
|
||||
*/
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static halclock_t hal_clock_f = LPC43XX_M4_CLK_IRC;
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||||
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||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
halclock_t halLPCGetSystemClock(void) {
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return hal_clock_f;
|
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}
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||||
|
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void halLPCSetSystemClock(const halclock_t new_frequency) {
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hal_clock_f = new_frequency;
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}
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||||
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void systick_adjust_period(const uint32_t counts_per_tick) {
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SysTick->LOAD = counts_per_tick;
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}
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||||
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/**
|
||||
* @brief Low level HAL driver initialization.
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*
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* @notapi
|
||||
*/
|
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void hal_lld_init(void) {
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LPC_CGU->BASE_M4_CLK.AUTOBLOCK = 1;
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LPC_CGU->BASE_M4_CLK.CLK_SEL = 1;
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|
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/* SysTick initialization using the system clock.*/
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systick_adjust_period(halLPCGetSystemClock() / CH_FREQUENCY - 1);
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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|
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/* DWT cycle counter enable.*/
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SCS_DEMCR |= SCS_DEMCR_TRCENA;
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DWT_CTRL |= DWT_CTRL_CYCCNTENA;
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}
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|
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/** @} */
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||||
176
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.h
Executable file
176
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.h
Executable file
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
Copyright (C) 2014 Jared Boone, ShareBrained Technology
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file LPC43xx_M4/hal_lld.h
|
||||
* @brief HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "lpc43xx_m4.h"
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||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
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||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Defines the support for realtime counters in the HAL.
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||||
*/
|
||||
#define HAL_IMPLEMENTS_COUNTERS TRUE
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||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
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||||
#define PLATFORM_NAME "LPC43xx M4"
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||||
/** @} */
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||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
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||||
#define DAC_IRQHandler Vector40 /**< DAC */
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||||
#define MAPP_IRQHandler Vector44 /**< Cortex-M0APP */
|
||||
#define DMA_IRQHandler Vector48 /**< DMA */
|
||||
#define Ethernet_IRQHandler Vector54 /**< Ethernet */
|
||||
#define SDIO_IRQHandler Vector58 /**< SD/MMC */
|
||||
#define LCD_IRQHandler Vector5C /**< LCD */
|
||||
#define USB0_IRQHandler Vector60 /**< USB0: OTG */
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||||
#define USB1_IRQHandler Vector64 /**< USB1 */
|
||||
#define SCT_IRQHandler Vector68 /**< SCT combined */
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||||
#define RITimer_IRQHandler Vector6C /**< RI Timer */
|
||||
#define Timer0_IRQHandler Vector70 /**< Timer 0 */
|
||||
#define Timer1_IRQHandler Vector74 /**< Timer 1 */
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||||
#define Timer2_IRQHandler Vector78 /**< Timer 2 */
|
||||
#define Timer3_IRQHandler Vector7C /**< Timer 3 */
|
||||
#define MCPWM_IRQHandler Vector80 /**< Motor control PWM */
|
||||
#define ADC0_IRQHandler Vector84 /**< ADC0 */
|
||||
#define I2C0_IRQHandler Vector88 /**< I2C0 */
|
||||
#define I2C1_IRQHandler Vector8C /**< I2C1 */
|
||||
#define SPI_IRQHandler Vector90 /**< SPI */
|
||||
#define ADC1_IRQHandler Vector94 /**< ADC1 */
|
||||
#define SSP0_IRQHandler Vector98 /**< SSP0 */
|
||||
#define SSP1_IRQHandler Vector9C /**< SSP1 */
|
||||
#define USART0_IRQHandler VectorA0 /**< USART0 */
|
||||
#define UART1_IRQHandler VectorA4 /**< UART1 */
|
||||
#define USART2_IRQHandler VectorA8 /**< USART2 */
|
||||
#define USART3_IRQHandler VectorAC /**< USART3 */
|
||||
#define I2S0_IRQHandler VectorB0 /**< I2S0 */
|
||||
#define I2S1_IRQHandler VectorB4 /**< I2S1 */
|
||||
#define SPIFI_IRQHandler VectorB8 /**< SPIFI */
|
||||
#define SGPIO_IRQHandler VectorBC /**< SGPIO */
|
||||
#define PIN_INT0_IRQHandler VectorC0 /**< GPIO pin interrupt 0 */
|
||||
#define PIN_INT1_IRQHandler VectorC4 /**< GPIO pin interrupt 1 */
|
||||
#define PIN_INT2_IRQHandler VectorC8 /**< GPIO pin interrupt 2 */
|
||||
#define PIN_INT3_IRQHandler VectorCC /**< GPIO pin interrupt 3 */
|
||||
#define PIN_INT4_IRQHandler VectorD0 /**< GPIO pin interrupt 4 */
|
||||
#define PIN_INT5_IRQHandler VectorD4 /**< GPIO pin interrupt 5 */
|
||||
#define PIN_INT6_IRQHandler VectorD8 /**< GPIO pin interrupt 6 */
|
||||
#define PIN_INT7_IRQHandler VectorDC /**< GPIO pin interrupt 7 */
|
||||
#define GINT0_IRQHandler VectorE0 /**< GPIO global interrupt 0 */
|
||||
#define GINT1_IRQHandler VectorE4 /**< GPIO global interrupt 1 */
|
||||
#define EventRouter_IRQHandler VectorE8 /**< Event router */
|
||||
#define C_CAN1_IRQHandler VectorEC /**< C_CAN1 */
|
||||
#define ATimer_IRQHandler VectorF8 /**< Alarm timer */
|
||||
#define RTC_IRQHandler VectorFC /**< RTC */
|
||||
#define WWDT_IRQHandler Vector104 /**< WWDT */
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||||
#define C_CAN0_IRQHandler Vector10C /**< C_CAN0 */
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#define QEI_IRQHandler Vector110 /**< QEI */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
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#define LPC43XX_M4_CLK_IRC 12000000
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|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
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/**
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* @brief Type representing a system clock frequency.
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||||
*/
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typedef uint32_t halclock_t;
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||||
|
||||
/**
|
||||
* @brief Type of the realtime free counter value.
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||||
*/
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||||
typedef uint32_t halrtcnt_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
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* @brief Returns the current value of the system free running counter.
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* @note This service is implemented by returning the content of the
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* DWT_CYCCNT register.
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*
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* @return The value of the system free running counter of
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* type halrtcnt_t.
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*
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* @notapi
|
||||
*/
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||||
#define hal_lld_get_counter_value() DWT_CYCCNT
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||||
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/**
|
||||
* @brief Realtime counter frequency.
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* @note The DWT_CYCCNT register is incremented directly by the system
|
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* clock so this function returns STM32_HCLK.
|
||||
*
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||||
* @return The realtime counter frequency of type halclock_t.
|
||||
*
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||||
* @notapi
|
||||
*/
|
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#define hal_lld_get_counter_frequency() halLPCGetSystemClock()
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||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
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#ifdef __cplusplus
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||||
extern "C" {
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#endif
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||||
void hal_lld_init(void);
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||||
void systick_adjust_period(const uint32_t counts_per_tick);
|
||||
halclock_t halLPCGetSystemClock(void);
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void halLPCSetSystemClock(const halclock_t new_frequency);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,254 @@
|
||||
/*
|
||||
ChibiOS/RT - Copyright (C) 2014 Jared Boone, ShareBrained Technology
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup lpc43xx_m4
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC43XX_M4_H
|
||||
#define __LPC43XX_M4_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Configuration_section_for_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< LPC43XX M4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< LPC43XX M4 uses 3 Bits for the Priority Levels*/
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
|
||||
/**
|
||||
* @brief LPC43XX M4 Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum IRQn {
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
/****** LPC43xx M4 specific Interrupt Numbers *****************************************************************/
|
||||
DAC_IRQn = 0, /*!< 16 DAC */
|
||||
M0CORE_IRQn = 1, /*!< 17 Cortex-M0APP; Latched TXEV; for M4-M0APP communication */
|
||||
DMA_IRQn = 2, /*!< 18 DMA */
|
||||
/* 3: 19 Reserved */
|
||||
/* 4: 20 ORed flash bank A, flash bank B, EEPROM interrupts */
|
||||
ETHERNET_IRQn = 5, /*!< 21 Ethernet */
|
||||
SDIO_IRQn = 6, /*!< 22 SD/MMC */
|
||||
LCD_IRQn = 7, /*!< 23 LCD */
|
||||
USB0_IRQn = 8, /*!< 24 OTG interrupt */
|
||||
USB1_IRQn = 9, /*!< 25 USB1 */
|
||||
SCT_IRQn = 10, /*!< 26 SCT combined interrupt */
|
||||
RITIMER_IRQn = 11, /*!< 27 RITIMER */
|
||||
TIMER0_IRQn = 12, /*!< 28 TIMER0 */
|
||||
TIMER1_IRQn = 13, /*!< 29 TIMER1 */
|
||||
TIMER2_IRQn = 14, /*!< 30 TIMER2 */
|
||||
TIMER3_IRQn = 15, /*!< 31 TIMER3 */
|
||||
MCPWM_IRQn = 16, /*!< 32 Motor control PWM */
|
||||
ADC0_IRQn = 17, /*!< 33 ADC0 */
|
||||
I2C0_IRQn = 18, /*!< 34 I2C0 */
|
||||
I2C1_IRQn = 19, /*!< 35 I2C1 */
|
||||
SPI_IRQn = 20, /*!< 36 SPI */
|
||||
ADC1_IRQn = 21, /*!< 37 ADC1 */
|
||||
SSP0_IRQn = 22, /*!< 38 SSP0 */
|
||||
SSP1_IRQn = 23, /*!< 39 SSP1 */
|
||||
USART0_IRQn = 24, /*!< 40 USART0 */
|
||||
UART1_IRQn = 25, /*!< 41 Combined UART interrupt with Modem interrupt */
|
||||
USART2_IRQn = 26, /*!< 42 USART2 */
|
||||
USART3_IRQn = 27, /*!< 43 Combined USART interrupt with IrDA interrupt */
|
||||
I2S0_IRQn = 28, /*!< 44 I2S0 */
|
||||
I2S1_IRQn = 29, /*!< 45 I2S1 */
|
||||
SPIFI_IRQn = 30, /*!< 46 SPIFI */
|
||||
SGPIO_IRQn = 31, /*!< 47 SGPIO */
|
||||
PIN_INT0_IRQn = 32, /*!< 48 GPIO pin interrupt 0 */
|
||||
PIN_INT1_IRQn = 33, /*!< 49 GPIO pin interrupt 1 */
|
||||
PIN_INT2_IRQn = 34, /*!< 50 GPIO pin interrupt 2 */
|
||||
PIN_INT3_IRQn = 35, /*!< 51 GPIO pin interrupt 3 */
|
||||
PIN_INT4_IRQn = 36, /*!< 52 GPIO pin interrupt 4 */
|
||||
PIN_INT5_IRQn = 37, /*!< 53 GPIO pin interrupt 5 */
|
||||
PIN_INT6_IRQn = 38, /*!< 54 GPIO pin interrupt 6 */
|
||||
PIN_INT7_IRQn = 39, /*!< 55 GPIO pin interrupt 7 */
|
||||
GINT0_IRQn = 40, /*!< 56 GPIO global interrupt 0 */
|
||||
GINT1_IRQn = 41, /*!< 57 GPIO global interrupt 1 */
|
||||
EVENTROUTER_IRQn = 42, /*!< 58 Event router */
|
||||
C_CAN_IRQn = 43, /*!< 59 C_CAN1 */
|
||||
/* 44: 60 Reserved */
|
||||
/* 45: 61 ADCHS combined */
|
||||
ATIMER_IRQn = 46, /*!< 62 Alarm timer */
|
||||
RTC_IRQn = 47, /*!< 63 RTC */
|
||||
/* 48: 64 Reserved */
|
||||
WWDT_IRQn = 49, /*!< 65 WWDT */
|
||||
/* 50: 66 TXEV instruction from the M0 subsystem core */
|
||||
C_CAN0_IRQn = 51, /*!< 67 C_CAN0 */
|
||||
QEI_IRQn = 52, /*!< 68 QEI */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "lpc43xx.inc"
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
/* NOTE: Override old, misbehaving SIMD #defines */
|
||||
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
|
||||
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
|
||||
|
||||
/* Overload of __SXTB16() to add ROR argument, since using __ROR() as an
|
||||
* argument to the existing __SXTB16() doesn't produce optimum/sane code.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t rm, uint32_t ror)
|
||||
{
|
||||
uint32_t rd;
|
||||
__ASM volatile ("sxtb16 %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
|
||||
return rd;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTH(uint32_t rm, uint32_t ror)
|
||||
{
|
||||
uint32_t rd;
|
||||
__ASM volatile ("sxth %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
|
||||
return rd;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLATB(uint32_t rm, uint32_t rs, uint32_t rn) {
|
||||
uint32_t rd;
|
||||
__ASM volatile ("smlatb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
|
||||
return rd;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLABB(uint32_t rm, uint32_t rs, uint32_t rn) {
|
||||
uint32_t rd;
|
||||
__ASM volatile("smlabb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
|
||||
return rd;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAH(uint32_t rn, uint32_t rm, uint32_t ror) {
|
||||
uint32_t rd;
|
||||
__ASM volatile("sxtah %0, %1, %2, ror %3" : "=r" (rd) : "r" (rn), "r" (rm), "I" (ror));
|
||||
return rd;
|
||||
}
|
||||
|
||||
/* NOTE: BFI is kinda weird because it modifies RD, copy __SMLALD style? */
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __BFI(uint32_t rd, uint32_t rn, uint32_t lsb, uint32_t width) {
|
||||
__ASM volatile("bfi %0, %1, %2, %3" : "+r" (rd) : "r" (rn), "I" (lsb), "I" (width));
|
||||
return rd;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBB(uint32_t op1, uint32_t op2) {
|
||||
uint32_t result;
|
||||
__ASM volatile ("smulbb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return result;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBT(uint32_t op1, uint32_t op2) {
|
||||
uint32_t result;
|
||||
__ASM volatile ("smulbt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return result;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTB(uint32_t op1, uint32_t op2) {
|
||||
uint32_t result;
|
||||
__ASM volatile ("smultb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return result;
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTT(uint32_t op1, uint32_t op2) {
|
||||
uint32_t result;
|
||||
__ASM volatile ("smultt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return result;
|
||||
}
|
||||
|
||||
#undef __SMLALD
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
__asm volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
#undef __SMLALDX
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
__asm volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
#undef __SMLSLD
|
||||
|
||||
__attribute__( ( always_inline ) ) static inline uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
__asm volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __LPC43XX_M4_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
13
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/platform.mk
Executable file
13
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/platform.mk
Executable file
@@ -0,0 +1,13 @@
|
||||
# List of all the LPC43xx M4 platform files.
|
||||
PLATFORMSRC = ${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx_M4/hal_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/gpt_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/i2c_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/pal_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/rtc_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/sdc_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/serial_lld.c \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx/spi_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx_M4 \
|
||||
${CHIBIOS_PORTAPACK}/os/hal/platforms/LPC43xx
|
||||
Reference in New Issue
Block a user