mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-24 21:21:50 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
131
firmware/chibios/os/hal/platforms/SPC564Axx/hal_lld.c
Executable file
131
firmware/chibios/os/hal/platforms/SPC564Axx/hal_lld.c
Executable file
@@ -0,0 +1,131 @@
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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||||
you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
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||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
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||||
*/
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/**
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* @file SPC564Axx/hal_lld.c
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* @brief SPC564Axx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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uint32_t n;
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/* The SRAM is parked on the load/store port, for some unknown reason it
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is defaulted on the instructions port and this kills performance.*/
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XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/
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/* The DMA priority is placed above the CPU priority in order to not
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starve I/O activities while the CPU is executing tight loops (FLASH
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and SRAM slave ports only).*/
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XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities:
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eDMA (4): 0 (highest)
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Core Instructions (0): 1
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Core Data (1): 2
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EBI (7): 3
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Flexray (6): 4 */
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XBAR.MPR2.R = 0x34000021; /* SRAM slave port priorities:
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eDMA (4): 0 (highest)
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Core Instructions (0): 1
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Core Data (1): 2
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EBI (7): 3
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FlexRay (6): 4 */
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/* Decrementer timer initialized for system tick use, note, it is
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initialized here because in the OSAL layer the system clock frequency
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is not yet known.*/
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n = SPC5_SYSCLK / CH_FREQUENCY;
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asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
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"mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
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"lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
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"mtspr 340, %%r3" /* TCR register. */
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: : [n] "r" (n) : "r3");
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/* TB counter enabled for debug and measurements.*/
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asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */
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"mtspr 1008, %%r3" /* HID0 register. */
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: : : "r3");
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/* INTC initialization, software vector mode, 4 bytes vectors, starting
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at priority 0.*/
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INTC.MCR.R = 0;
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INTC.CPR.R = 0;
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INTC.IACKR.R = (uint32_t)_vectors;
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}
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/**
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* @brief SPC563 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h and
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* @p hal_lld.h
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* @note This function must be invoked only after the system reset.
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*
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* @special
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*/
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void spc_clock_init(void) {
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/* Setting up RAM/Flash wait states and the prefetching bits.*/
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ECSM.MUDCR.R = SPC5_RAM_WS;
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FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
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FLASH_A.BIUCR2.R = 0;
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FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
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FLASH_B.BIUCR2.R = 0;
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#if !SPC5_NO_INIT
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/* PLL activation.*/
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FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
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FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
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#if !SPC5_CLK_BYPASS
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FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
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FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
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FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
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FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
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while (!FMPLL.SYNSR.B.LOCK)
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;
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FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
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#endif /* !SPC5_CLK_BYPASS */
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#endif /* !SPC5_NO_INIT */
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}
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/** @} */
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278
firmware/chibios/os/hal/platforms/SPC564Axx/hal_lld.h
Executable file
278
firmware/chibios/os/hal/platforms/SPC564Axx/hal_lld.h
Executable file
@@ -0,0 +1,278 @@
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
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|
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http://www.apache.org/licenses/LICENSE-2.0
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|
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Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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See the License for the specific language governing permissions and
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||||
limitations under the License.
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*/
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/**
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* @file SPC564Axx/hal_lld.h
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* @brief SPC564Axx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SPC5_XOSC_CLK.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "xpc564a.h"
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#include "spc564a_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "SPC564Axx Powertrain"
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/**
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* @name ESYNCR2 register definitions
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* @{
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*/
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#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
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#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
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#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
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#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
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/** @} */
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/**
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* @name BIUCR register definitions
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* @{
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*/
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#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
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#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
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#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
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#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
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#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
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#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
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#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
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#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
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#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
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#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
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#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
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#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
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#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
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#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
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#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
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#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
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#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
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#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
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#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
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#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
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#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
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#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
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#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
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#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
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#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
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#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
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#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
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#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
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#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
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#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
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#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
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#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
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#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
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#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
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#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
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#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
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#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
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#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Disables the clocks initialization in the HAL.
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*/
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#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
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#define SPC5_NO_INIT FALSE
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#endif
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/**
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* @brief Clock bypass.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
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#define SPC5_CLK_BYPASS FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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* @brief External clock pre-divider.
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||||
* @note Must be in range 1...15.
|
||||
*/
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#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_CLK_PREDIV_VALUE 2
|
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#endif
|
||||
|
||||
/**
|
||||
* @brief Multiplication factor divider.
|
||||
* @note Must be in range 32...96.
|
||||
*/
|
||||
#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
|
||||
#define SPC5_CLK_MFD_VALUE 75
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Reduced frequency divider.
|
||||
*/
|
||||
#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
|
||||
#define SPC5_CLK_RFD RFD_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Flash buffer and prefetching settings.
|
||||
* @note Please refer to the SPC564Axx reference manual about the meaning
|
||||
* of the following bits, if in doubt DO NOT MODIFY IT.
|
||||
* @note Do not specify the APC, WWSC, RWSC bits in this value because
|
||||
* those are calculated from the system clock and ORed with this
|
||||
* value.
|
||||
*/
|
||||
#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
|
||||
#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
|
||||
BIUCR_MASTER4_PREFETCH | \
|
||||
BIUCR_MASTER0_PREFETCH | \
|
||||
BIUCR_DPFEN | \
|
||||
BIUCR_IPFEN | \
|
||||
BIUCR_PFLIM_ON_MISS | \
|
||||
BIUCR_BFEN)
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(SPC564Axx_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
|
||||
#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
|
||||
#endif
|
||||
|
||||
#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
|
||||
#error "invalid SPC5_CLK_MFD_VALUE value specified"
|
||||
#endif
|
||||
|
||||
#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
|
||||
(SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
|
||||
#error "invalid SPC5_CLK_RFD value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL input divider.
|
||||
*/
|
||||
#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
|
||||
|
||||
/**
|
||||
* @brief PLL multiplier.
|
||||
*/
|
||||
#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLL output clock.
|
||||
*/
|
||||
#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
|
||||
SPC5_CLK_MFD_VALUE)
|
||||
|
||||
#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
|
||||
#error "VCO frequency out of the acceptable range (256...512)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL output clock.
|
||||
*/
|
||||
#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
|
||||
#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
|
||||
#else
|
||||
#define SPC5_SYSCLK SPC5_XOSC_CLK
|
||||
#endif
|
||||
|
||||
#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
|
||||
#error "System clock above maximum rated frequency (150MHz)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Flash wait states are a function of the system clock.
|
||||
*/
|
||||
#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
|
||||
#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3)
|
||||
#elif SPC5_SYSCLK <= 61000000
|
||||
#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3)
|
||||
#elif SPC5_SYSCLK <= 90000000
|
||||
#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3)
|
||||
#elif SPC5_SYSCLK <= 123000000
|
||||
#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3)
|
||||
#else
|
||||
#define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RAM wait states are a function of the system clock.
|
||||
*/
|
||||
#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
|
||||
#define SPC5_RAM_WS 0
|
||||
#else
|
||||
#define SPC5_RAM_WS 0x40000000
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#include "spc5_edma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void spc_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
13
firmware/chibios/os/hal/platforms/SPC564Axx/platform.mk
Executable file
13
firmware/chibios/os/hal/platforms/SPC564Axx/platform.mk
Executable file
@@ -0,0 +1,13 @@
|
||||
# List of all the SPC564Axx platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC564Axx \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \
|
||||
${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1
|
||||
64
firmware/chibios/os/hal/platforms/SPC564Axx/spc564a_registry.h
Executable file
64
firmware/chibios/os/hal/platforms/SPC564Axx/spc564a_registry.h
Executable file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC564Axx/spc564a_registry.h
|
||||
* @brief SPC564Axx capabilities registry.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _SPC563M_REGISTRY_H_
|
||||
#define _SPC563M_REGISTRY_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name SPC564Axx capabilities
|
||||
* @{
|
||||
*/
|
||||
/* eDMA attributes.*/
|
||||
#define SPC5_HAS_EDMA TRUE
|
||||
#define SPC5_EDMA_NCHANNELS 64
|
||||
#define SPC5_EDMA_HAS_MUX FALSE
|
||||
|
||||
/* eQADC attributes.*/
|
||||
#define SPC5_HAS_EQADC TRUE
|
||||
|
||||
/* eSCI attributes.*/
|
||||
#define SPC5_HAS_ESCIA TRUE
|
||||
#define SPC5_ESCIA_HANDLER vector146
|
||||
#define SPC5_ESCIA_NUMBER 146
|
||||
|
||||
#define SPC5_HAS_ESCIB TRUE
|
||||
#define SPC5_ESCIB_HANDLER vector149
|
||||
#define SPC5_ESCIB_NUMBER 149
|
||||
|
||||
#define SPC5_HAS_ESCIC TRUE
|
||||
#define SPC5_ESCIC_HANDLER vector473
|
||||
#define SPC5_ESCIC_NUMBER 473
|
||||
|
||||
/* SIU attributes.*/
|
||||
#define SPC5_HAS_SIU TRUE
|
||||
#define SPC5_SIU_SUPPORTS_PORTS FALSE
|
||||
/** @} */
|
||||
|
||||
#endif /* _SPC563M_REGISTRY_H_ */
|
||||
|
||||
/** @} */
|
||||
27
firmware/chibios/os/hal/platforms/SPC564Axx/typedefs.h
Executable file
27
firmware/chibios/os/hal/platforms/SPC564Axx/typedefs.h
Executable file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SPC564Axx/typedefs.h
|
||||
* @brief Dummy typedefs file.
|
||||
*/
|
||||
|
||||
#ifndef _TYPEDEFS_H_
|
||||
#define _TYPEDEFS_H_
|
||||
|
||||
#include "chtypes.h"
|
||||
|
||||
#endif /* _TYPEDEFS_H_ */
|
||||
6377
firmware/chibios/os/hal/platforms/SPC564Axx/xpc564a.h
Executable file
6377
firmware/chibios/os/hal/platforms/SPC564Axx/xpc564a.h
Executable file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user