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920b98f7c9
mayhem-firmware/hardware/portapack_h1/audio.sch
Maescool 920b98f7c9 Upstream merge to make new revision of PortaPack work (#206) 
* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts
2019-01-11 06:56:21 +00:00

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EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 6
Title "PortaPack H1"
Date "2018-08-20"
Rev "20180820"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
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Text Notes 2300 2500 0 60 ~ 0
I2C Addresses on HackRF I2C bus (I2C0?):\n\n0b1100000: Si5351C-B\n0b0010010: AK4951 audio codec
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U 1 1 58D9A87F
P 9100 3200
F 0 "#PWR017" H 9100 3200 30 0001 C CNN
F 1 "GND" H 9100 3130 30 0001 C CNN
F 2 "" H 9100 3200 60 0000 C CNN
F 3 "" H 9100 3200 60 0000 C CNN
1 9100 3200
0 1 1 0
$EndComp
Text Label 9600 2200 0 60 ~ 0
LHPOUT_X
Text Label 9600 2100 0 60 ~ 0
RHPOUT_X
Text Label 9600 2000 0 60 ~ 0
GND_X
Text Label 9600 1900 0 60 ~ 0
MIC_X
Text Label 4900 6400 0 60 ~ 0
MIC
Text Label 10300 3100 0 60 ~ 0
LHPOUT_X
Text Label 10300 3300 0 60 ~ 0
MIC_X
Text Label 10300 3200 0 60 ~ 0
GND_X
Text Label 10300 3400 0 60 ~ 0
RHPOUT_X
Text Label 8700 3100 0 60 ~ 0
LHPOUT
Text Label 8700 3400 0 60 ~ 0
RHPOUT
Text Label 8700 3300 0 60 ~ 0
MIC
$Comp
L tp:TP TP1
U 1 1 58EDDA01
P 3700 4800
F 0 "TP1" H 3500 4800 60 0000 C CNN
F 1 "TP" H 3650 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 3700 4800 60 0001 C CNN
F 3 "" H 3700 4800 60 0001 C CNN
1 3700 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP2
U 1 1 58EDDAEE
P 4500 4800
F 0 "TP2" H 4300 4800 60 0000 C CNN
F 1 "TP" H 4450 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4500 4800 60 0001 C CNN
F 3 "" H 4500 4800 60 0001 C CNN
1 4500 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP3
U 1 1 58EDDB69
P 4600 4800
F 0 "TP3" H 4400 4800 60 0000 C CNN
F 1 "TP" H 4550 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4600 4800 60 0001 C CNN
F 3 "" H 4600 4800 60 0001 C CNN
1 4600 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP4
U 1 1 58EDDC3F
P 4900 4800
F 0 "TP4" H 4700 4800 60 0000 C CNN
F 1 "TP" H 4850 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4900 4800 60 0001 C CNN
F 3 "" H 4900 4800 60 0001 C CNN
1 4900 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP5
U 1 1 58EDDCA8
P 5000 4800
F 0 "TP5" H 4800 4800 60 0000 C CNN
F 1 "TP" H 4950 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 5000 4800 60 0001 C CNN
F 3 "" H 5000 4800 60 0001 C CNN
1 5000 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP6
U 1 1 58EDDD10
P 5100 4800
F 0 "TP6" H 4900 4800 60 0000 C CNN
F 1 "TP" H 5050 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 5100 4800 60 0001 C CNN
F 3 "" H 5100 4800 60 0001 C CNN
1 5100 4800
0 -1 -1 0
$EndComp
$Comp
L header:HEADER_1X3 J1
U 1 1 58F82DA0
P 5800 2100
F 0 "J1" H 5800 1850 60 0000 C CNN
F 1 "HEADER_1X3" H 5800 1850 60 0001 C CNN
F 2 "jst:JST_S3B-PH-SM4-TB" H 5800 1900 60 0001 C CNN
F 3 "http://www.jst-mfg.com/product/pdf/eng/ePH.pdf" H 5800 1900 60 0001 C CNN
F 4 "JST" H 5800 2100 60 0001 C CNN "Mfr"
F 5 "S3B-PH-SM4-TB" H 5800 2100 60 0001 C CNN "Part"
F 6 "DNP" H 5800 2100 60 0000 C CNN "DNP"
1 5800 2100
1 0 0 1
$EndComp
$Comp
L power:GND #PWR018
U 1 1 58F8315C
P 5400 2100
F 0 "#PWR018" H 5400 2100 30 0001 C CNN
F 1 "GND" H 5400 2030 30 0001 C CNN
F 2 "" H 5400 2100 60 0000 C CNN
F 3 "" H 5400 2100 60 0000 C CNN
1 5400 2100
0 1 1 0
$EndComp
Wire Wire Line
9000 1900 10300 1900
Wire Wire Line
4600 1500 6400 1500
Wire Wire Line
4700 1600 6800 1600
Connection ~ 6400 1500
Wire Wire Line
5200 2900 5200 2800
Wire Wire Line
3800 3400 3900 3400
Wire Wire Line
2700 3800 2800 3800
Wire Wire Line
5700 3400 5800 3400
Wire Wire Line
5100 2900 5100 2800
Wire Wire Line
3900 3700 4000 3700
Wire Wire Line
4800 2900 4800 2800
Wire Wire Line
1000 6900 1200 6900
Connection ~ 1200 6900
Wire Wire Line
3200 6900 3400 6900
Connection ~ 3400 6900
Wire Wire Line
4300 6900 4500 6900
Connection ~ 4500 6900
Wire Wire Line
4500 2600 4500 2900
Wire Wire Line
3900 2600 4500 2600
Wire Wire Line
4000 3500 3100 3500
Wire Wire Line
3100 3500 3100 3000
Wire Wire Line
3100 3000 2800 3000
Wire Wire Line
2800 3600 4000 3600
Wire Wire Line
5700 4000 5800 4000
Wire Wire Line
5800 4100 5700 4100
Wire Wire Line
4700 2900 4700 1600
Wire Wire Line
4600 1500 4600 2900
Wire Wire Line
5700 3900 5800 3900
Wire Wire Line
5700 3800 6700 3800
Wire Wire Line
5700 3700 6700 3700
Wire Wire Line
5700 3600 6700 3600
Wire Wire Line
5700 3500 5800 3500
Wire Wire Line
5200 4600 5200 4700
Wire Wire Line
5200 4700 5400 4700
Wire Wire Line
4800 5300 4800 4600
Wire Wire Line
5000 6000 4700 6000
Connection ~ 4700 6000
Connection ~ 5400 4700
Wire Wire Line
4700 6400 5200 6400
Wire Wire Line
4000 4300 3900 4300
Wire Wire Line
9000 2000 10300 2000
Wire Wire Line
9200 3200 9100 3200
Wire Wire Line
9700 3800 9700 3700
Wire Wire Line
9000 2100 10300 2100
Wire Wire Line
5000 5300 4800 5300
Connection ~ 6800 1600
Wire Wire Line
9000 2200 10100 2200
Wire Wire Line
10100 2200 10100 2400
Wire Wire Line
10100 2400 10300 2400
Wire Wire Line
10900 3100 10200 3100
Wire Wire Line
10900 3200 10200 3200
Wire Wire Line
10900 3300 10200 3300
Wire Wire Line
10900 3400 10200 3400
Wire Wire Line
8600 3400 9200 3400
Wire Wire Line
8600 3300 9200 3300
Wire Wire Line
8600 3100 9200 3100
Wire Wire Line
4500 4700 4500 4600
Wire Wire Line
4600 4700 4600 4600
Wire Wire Line
4900 4700 4900 4600
Wire Wire Line
5000 4700 5000 4600
Wire Wire Line
5100 4700 5100 4600
Wire Wire Line
3700 4100 4000 4100
Connection ~ 3900 3400
Wire Wire Line
3700 4100 3700 4700
Wire Wire Line
4000 4000 3500 4000
Wire Wire Line
3500 4000 3500 4300
Wire Wire Line
4000 3900 3400 3900
Wire Wire Line
3400 3900 3400 4000
Wire Wire Line
2800 3800 2800 4000
Connection ~ 2800 3800
Connection ~ 2800 4000
Wire Wire Line
5500 2000 4900 2000
Wire Wire Line
4900 2000 4900 2900
Wire Wire Line
5500 2200 5000 2200
Wire Wire Line
5000 2200 5000 2900
Wire Wire Line
5500 2100 5400 2100
$Comp
L passive:RPACK4 RP1
U 1 1 58F9564A
P 6900 3750
F 0 "RP1" H 6900 4000 60 0000 C CNN
F 1 "220R" H 6900 3500 60 0000 C CNN
F 2 "ipc_rescax:IPC_RESCAXS8P80_320X160X60L30X45N" H 6900 3750 60 0001 C CNN
F 3 "https://industrial.panasonic.com/cdbs/www-data/pdf/AOC0000/AOC0000C14.pdf" H 6900 3750 60 0001 C CNN
F 4 "Panasonic" H 6900 3750 60 0001 C CNN "Mfr"
F 5 "EXB-38V221JV" H 6900 3750 60 0001 C CNN "Part"
1 6900 3750
1 0 0 -1
$EndComp
Wire Wire Line
6700 3900 6600 3900
Wire Wire Line
6600 3900 6600 4700
Wire Wire Line
7100 3600 7200 3600
Wire Wire Line
7200 3700 7100 3700
Wire Wire Line
7100 3800 7200 3800
Wire Wire Line
7200 3900 7100 3900
Text Label 6200 3600 0 60 ~ 0
BICK_R
Text Label 6200 3700 0 60 ~ 0
LRCK_R
Text Label 6200 3800 0 60 ~ 0
SDTO_R
Text Label 5600 4700 0 60 ~ 0
PDN#_R
Text Label 5100 2000 0 60 ~ 0
SPP
Text Label 5100 2200 0 60 ~ 0
SPN
Wire Wire Line
2100 6900 2300 6900
Text Notes 1800 7700 0 60 ~ 0
No 10U on DVDD, very near regulator 10U.
Text Notes 4250 7700 0 60 ~ 0
No 10U on SVDD to comply with USB inrush spec.
Wire Wire Line
6400 1500 7600 1500
Wire Wire Line
1200 6900 1600 6900
Wire Wire Line
3400 6900 3800 6900
Wire Wire Line
4500 6900 4900 6900
Wire Wire Line
4700 6000 4700 6400
Wire Wire Line
5400 4700 6600 4700
Wire Wire Line
6800 1600 7600 1600
Wire Wire Line
3900 3400 4000 3400
Wire Wire Line
2800 3800 4000 3800
Wire Wire Line
2800 4000 2800 4300
Wire Wire Line
3900 2600 3900 2950
Wire Wire Line
3900 3250 3900 3400
Wire Wire Line
2800 3000 2800 3150
Wire Wire Line
2800 3600 2800 3450
Wire Wire Line
2800 4000 2950 4000
Wire Wire Line
2800 4300 2950 4300
Wire Wire Line
3250 4300 3500 4300
Wire Wire Line
3250 4000 3400 4000
Wire Wire Line
4700 4600 4700 5450
Wire Wire Line
4700 5750 4700 6000
Wire Wire Line
5000 5300 5000 5500
Wire Wire Line
5000 5800 5000 6000
Wire Wire Line
5400 5200 5400 5400
Wire Wire Line
5400 4700 5400 4900
Wire Wire Line
6400 2550 6400 2750
Wire Wire Line
6400 2000 6400 2250
Wire Wire Line
6400 1500 6400 1700
Wire Wire Line
6800 1600 6800 1700
Wire Wire Line
6800 2000 6800 2250
Wire Wire Line
6800 2550 6800 2750
Wire Wire Line
1200 6900 1200 7050
Wire Wire Line
1200 7350 1200 7500
Wire Wire Line
1600 7350 1600 7500
Wire Wire Line
1600 6900 1600 7050
Wire Wire Line
2300 6900 2300 7050
Wire Wire Line
2300 7350 2300 7500
Wire Wire Line
3400 7350 3400 7500
Wire Wire Line
3400 6900 3400 7050
Wire Wire Line
3800 6900 3800 7050
Wire Wire Line
3800 7350 3800 7500
Wire Wire Line
4500 7350 4500 7500
Wire Wire Line
4500 6900 4500 7050
Wire Wire Line
4900 6900 4900 7050
Wire Wire Line
4900 7350 4900 7500
$EndSCHEMATC
Reference in New Issue View Git Blame Copy Permalink