mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-14 20:18:13 +00:00
146 lines
3.8 KiB
C++
146 lines
3.8 KiB
C++
/*
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* Copyright (C) 2016 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpld_xilinx.hpp"
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namespace cpld {
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namespace xilinx {
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void XC2C64A::write_sram(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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enable();
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shift_ir(instruction_t::ISC_WRITE);
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for(const auto& block : blocks) {
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tap.state(state_t::shift_dr);
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tap.shift({ block.data.data(), block_length }, false);
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tap.shift({ &block.id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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}
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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}
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bool XC2C64A::verify_sram(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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enable();
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shift_ir(instruction_t::ISC_SRAM_READ);
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// Prime the operation with a read of an empty row.
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const jtag::tap::bits_t empty_row { block_length };
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tap.state(state_t::shift_dr);
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tap.shift(empty_row, false);
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auto error = false;
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for(const auto& block : blocks) {
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tap.shift({ &block.id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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tap.state(state_t::shift_dr);
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error |= tap.shift(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length }, false);
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}
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// Redundant operation to finish the row.
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tap.shift({ &blocks[0].id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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return !error;
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}
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bool XC2C64A::verify_eeprom(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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bypass();
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enable();
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shift_ir(instruction_t::ISC_READ);
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const jtag::tap::bits_t empty_row { block_length };
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auto error = false;
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for(const auto& block : blocks) {
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tap.set_end_dr(state_t::pause_dr);
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tap.shift_dr({ &block.id, block_id_length });
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tap.set_end_ir(state_t::run_test_idle);
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tap.wait(state_t::pause_dr, state_t::pause_dr, 20);
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tap.set_end_ir(state_t::run_test_idle);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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error |= tap.shift_dr(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length });
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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}
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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return !error;
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}
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bool XC2C64A::shift_ir(const instruction_t instruction) {
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const ir_t ir_buffer = toUType(instruction);
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const jtag::tap::bits_t bits { &ir_buffer, ir_length };
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return tap.shift_ir(bits);
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}
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void XC2C64A::reset() {
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tap.state(state_t::test_logic_reset);
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tap.state(state_t::run_test_idle);
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}
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void XC2C64A::enable() {
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shift_ir(instruction_t::ISC_ENABLE);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 800);
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}
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void XC2C64A::disable() {
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shift_ir(instruction_t::ISC_DISABLE);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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}
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bool XC2C64A::bypass() {
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return shift_ir(instruction_t::BYPASS);
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}
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} /* namespace xilinx */
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} /* namespace cpld */
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