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JTAG: Code to manage HackRF CPLD interactions.
This commit is contained in:
Jared Boone
parent
71c7f543c5
commit
4cc356f325
145
firmware/common/cpld_xilinx.cpp
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145
firmware/common/cpld_xilinx.cpp
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/*
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* Copyright (C) 2016 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpld_xilinx.hpp"
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namespace cpld {
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namespace xilinx {
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void XC2C64A::write_sram(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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enable();
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shift_ir(instruction_t::ISC_WRITE);
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for(const auto& block : blocks) {
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tap.state(state_t::shift_dr);
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tap.shift({ block.data.data(), block_length }, false);
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tap.shift({ &block.id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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}
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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}
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bool XC2C64A::verify_sram(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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enable();
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shift_ir(instruction_t::ISC_SRAM_READ);
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// Prime the operation with a read of an empty row.
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const jtag::tap::bits_t empty_row { block_length };
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tap.state(state_t::shift_dr);
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tap.shift(empty_row, false);
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auto error = false;
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for(const auto& block : blocks) {
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tap.shift({ &block.id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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tap.state(state_t::shift_dr);
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error |= tap.shift(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length }, false);
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}
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// Redundant operation to finish the row.
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tap.shift({ &blocks[0].id, block_id_length }, true);
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tap.state(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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return !error;
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}
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bool XC2C64A::verify_eeprom(const verify_blocks_t& blocks) {
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tap.set_repeat(0);
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tap.set_end_ir(state_t::run_test_idle);
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tap.set_end_dr(state_t::run_test_idle);
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reset();
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bypass();
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enable();
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shift_ir(instruction_t::ISC_READ);
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const jtag::tap::bits_t empty_row { block_length };
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auto error = false;
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for(const auto& block : blocks) {
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tap.set_end_dr(state_t::pause_dr);
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tap.shift_dr({ &block.id, block_id_length });
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tap.set_end_ir(state_t::run_test_idle);
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tap.wait(state_t::pause_dr, state_t::pause_dr, 20);
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tap.set_end_ir(state_t::run_test_idle);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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error |= tap.shift_dr(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length });
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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}
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disable();
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bypass();
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tap.state(state_t::test_logic_reset);
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return !error;
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}
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bool XC2C64A::shift_ir(const instruction_t instruction) {
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const ir_t ir_buffer = toUType(instruction);
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const jtag::tap::bits_t bits { &ir_buffer, ir_length };
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return tap.shift_ir(bits);
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}
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void XC2C64A::reset() {
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tap.state(state_t::test_logic_reset);
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tap.state(state_t::run_test_idle);
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}
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void XC2C64A::enable() {
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shift_ir(instruction_t::ISC_ENABLE);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 800);
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}
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void XC2C64A::disable() {
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shift_ir(instruction_t::ISC_DISABLE);
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tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100);
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}
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bool XC2C64A::bypass() {
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return shift_ir(instruction_t::BYPASS);
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}
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} /* namespace xilinx */
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} /* namespace cpld */
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122
firmware/common/cpld_xilinx.hpp
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122
firmware/common/cpld_xilinx.hpp
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@ -0,0 +1,122 @@
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/*
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* Copyright (C) 2016 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __CPLD_XILINX_H__
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#define __CPLD_XILINX_H__
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#include "jtag_tap.hpp"
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#include "utility.hpp"
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#include <cstdint>
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#include <cstddef>
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#include <array>
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namespace cpld {
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namespace xilinx {
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using jtag::tap::state_t;
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class XC2C64A {
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public:
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using block_id_t = uint8_t;
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static constexpr size_t block_length = 274;
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static constexpr size_t blocks_count = 98;
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static constexpr size_t block_bytes = (block_length + 7) >> 3;
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struct verify_block_t {
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block_id_t id;
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std::array<uint8_t, block_bytes> data;
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std::array<uint8_t, block_bytes> mask;
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};
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struct program_block_t {
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block_id_t id;
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std::array<uint8_t, block_bytes> data;
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};
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using verify_blocks_t = std::array<verify_block_t, blocks_count>;
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constexpr XC2C64A(
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jtag::Target& jtag_interface
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) : tap { jtag_interface }
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{
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}
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void write_sram(const verify_blocks_t& blocks);
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bool verify_sram(const verify_blocks_t& blocks);
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bool verify_eeprom(const verify_blocks_t& blocks);
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private:
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static constexpr size_t idcode_length = 32;
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using idcode_t = uint32_t;
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static constexpr size_t ir_length = 8;
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static constexpr size_t block_id_length = 7;
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static constexpr idcode_t idcode = 0x06e58093;
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static constexpr idcode_t idcode_mask = 0x0fff8fff;
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using ir_t = uint8_t;
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jtag::tap::TAPMachine tap;
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enum class instruction_t : ir_t {
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INTEST = 0b00000010, // -> boundary-scan
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BYPASS = 0b11111111, // -> bypass
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SAMPLE = 0b00000011, // -> boundary-scan
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EXTEST = 0b00000000, // -> boundary-scan
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IDCODE = 0b00000001, // -> device ID
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USERCODE = 0b11111101, // -> device ID
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HIGHZ = 0b11111100, // -> bypass
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ISC_ENABLE_CLAMP = 0b11101001, // -> ISC shift
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ISC_ENABLE_OTF = 0b11100100, // -> ISC shift
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ISC_ENABLE = 0b11101000, // -> ISC shift
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ISC_SRAM_READ = 0b11100111, // -> ISC shift
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ISC_WRITE = 0b11100110, // -> ISC shift, alias ISC_SRAM_WRITE
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ISC_ERASE = 0b11101101, // -> ISC shift
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ISC_PROGRAM = 0b11101010, // -> ISC shift
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ISC_READ = 0b11101110, // -> ISC shift, alias ISC_VERIFY
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ISC_INIT = 0b11110000, // -> ISC shift
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ISC_DISABLE = 0b11000000, // -> ISC shift
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TEST_ENABLE = 0b00010001, // alias Private1
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BULKPROG = 0b00010010, // alias Private2
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ERASE_ALL = 0b00010100, // alias Private4
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MVERIFY = 0b00010011, // alias Private3
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TEST_DISABLE = 0b00010101, // alias Private5
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ISC_NOOP = 0b11100000, // -> bypass
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};
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bool shift_ir(const instruction_t instruction);
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void reset();
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void enable();
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void disable();
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bool bypass();
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};
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} /* namespace xilinx */
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} /* namespace cpld */
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#endif/*__CPLD_XILINX_H__*/
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